Abstract: A substantially zero overhead mutual-exclusion apparatus and method (90, 120) is provided that allows concurrent reading and updating data while maintaining data coherency. That is, a data reading process executes the same sequence of instructions that would be executed if the data were never updated. Rather than depending exclusively on overhead-imposing locks, this mutual-exclusion mechanism tracks an execution history (138) of a thread (16, 112) to determine safe times for processing a current generation (108, 130, 131) of data updates while a next generation (110, 132, 133) of data updates is concurrently being saved. A thread is any locus of control, such as a processor. A summary of thread activity (106, 122) tracks which threads have passed through a quiescent state after the current generation of updates was started.

Abstract: Apparatus and a method for easily expanding the effective width of the data words of a CAM without significantly increasing the basic width of the data storage registers or comparand register. A plurality of comparison blocks each include a register for data words having a predetermined width. Each data word includes a start bit, which indicates that a data word is the first data word of a much larger data word (or data line), and a chain bit, which indicates that a match has occurred between part of a comparand and the data word stored in the register. A maskable comparator provides a match output signal. The start bit is initially loaded into the chain-bit register for a data word. A latch is provided for storing the value of the chain bit from a preceding register into the chain-bit register of a following register. A priority encoder receives the match output signals from each of the comparators of the comparison blocks to identify the highest-priority comparison block, and the corresponding data line.

Abstract: A method and apparatus for prechecking (probing) the validity of an access request for writing result data to an external system prior to executing the instruction that generates the result is provided. This allows instruction execution to continue uninterrupted in the event that the write is allowed. The microprocessor's Address Unit issues a "probe" request to the Memory Management Unit (MMU) via an internal bus while saving the instruction's virtual address in a virtual address buffer local to the Address Unit. The MMU checks the validity of the "probe" request without converting the virtual address to a physical address and issues an access grant signal which is saved by the microprocessor's Execution Unit for subsequent use. The Execution Unit processes the data in parallel to the MMU checking the validity of the probe request.

Abstract: Each card slot in a computer system receives a different ordering of address lines than each of the other card slots so that the ordering of the address lines at each card slot is indicative of its physical address relative to the other card slots. Means responsive to codes provided on at least selected ones of the address lines for establishing the hard and soft physical addresses of cards to be inserted into the slots may be provided.

Abstract: A method and means is disclosed for dynamically partitioning an LRU cache partitioned into a global cache storing referenced objects of k different data types and k local caches storing objects of a single type. Referenced objects are stored in the MRU position of the global cache and overflow is managed by destaging the LRU object from the global to the local cache having the same data type. Dynamic partitioning is accomplished by recursively creating and maintaining from a trace of objects an LRU list of referenced objects and associated data structures for each subcache, creating and maintaining a multi-planar array of partition distribution data from the lists and the trace as a collection of all possible of maximum and minimum subcache sizing, optimally resizing the subcache partitions by applying a dynamic programming heuristic to the multiplanar array, and readjusting the partitions accordingly.

Abstract: A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has an associated cache control system. When a processor's cache control system does not have a required memory location in the cache memory, it broadcasts a memory request packet across the memory bus for the required data. If an owned cache line is being replaced, the cache control system copies the old cache line data to the pending write-back cache controller which is responsible for the write-backs of owned cache lines to main memory. The cache control system then transfers ownership of the old replaced cache line to the pending write-back controller.

Abstract: A fault-tolerant high performance mirrored disk subsystem is described which has an improved disk writing scheme that provides high throughput for random disk writes and at the same time guarantees high performance for disk reads. The subsystem also has an improved recovery mechanism which provides fast recovery in the event that one of the mirrored disks fails and during such recovery provides the same performance as during non-recovery periods.Data blocks or pages which are to be written to disk are temporarily accumulated and sorted (or scheduled) into an order (or schedule) which can be written to disk efficiently, which in a preferred embodiment is in accordance with the physical location on disk at which each such block will be written. This also generally corresponds to an order which is encountered by a writ head during a physical scan of a disk. The disks of a mirrored pair are operated out of phase with each other, so that one will be in read mode while the other is in write mode.

Abstract: A computer system provides transactional memory operations, in which a selected data item in a shared memory is referenced by a CPU in local storage (such as a write-back cache). The CPU performs some operation to alter or use the data item while it is in local memory, and meanwhile monitors the bus to the shared memory to see if another processor references the selected location (as by a snoop mechanism); if so, a status bit is toggled to indicate that the transaction must be scrubbed. When the operation has been completed by the CPU, it attempts to "commit" the transaction, and this includes checking the status bit; if the bit has been toggled, the transaction aborts, the data item is invalidated in local memory, and the selected location in shared memory is not affected. If the status bit has not been toggled, the transaction is committed and the altered data item becomes visible to the other processors, and may be written back to the shared memory.

Abstract: An information processing apparatus with an address extension function includes a set of address adders for performing address addition with respect to a first fraction of an address for an instruction and/or a data, which fraction corresponds to the not extended bit portion of the address, and a set of domain registers for storing a second fraction of the address for an instruction or an operand, which fraction corresponds to the extended bit portion of the address. If address extension is not made, address translation into a real address is performed using a virtual address obtained through addition operation by the address adder and in accordance with a conventional not address extended program. If address extension is made, address translation into a real address is performed using a virtual address obtained by concatinating the addition result by the address adder with the content of the domain register.

Abstract: An external memory cartridge for replaceable connection with a video game main unit contains a security device that prevents unauthorized memory cartridges from playing on the game main unit. The video game main unit connects to a television receiver, and includes at least one video graphics processing arrangement that controls the television receiver to display a changing picture defined by video game software contained in the external memory cartridge. The external memory cartridge has a cartridge housing that contains a video game memory device and a security device. The video game memory device contains video game software. An electrical connector couples the video game memory device with said video game main unit to permit the video game main unit to access and execute the video game software. The security device includes at least one input terminal and at least one output terminal connected to said electrical connector.

Abstract: A chipset is provided which permits reading and writing to cache tag memory for testing purposes and for writing non-cacheable tags into tag RAM entries to effectively invalidate the corresponding cache data entries.

Abstract: A method for reading a multiple byte data element stored in both first and second memories. Selected bytes of the data element are invalidated in the first memory. Valid bytes from the first memory are combined with remaining bytes from the second memory in response to a read request.

Abstract: A main memory has a plurality of divided storage areas. A central processing unit saves data from each storage area of the main memory into an auxiliary memory during a normal operation of a computer system, and sets a flag corresponding to each storage area, from which the data is saved, in a state indicating the end of a save operation. In addition, when data stored in the main memory is updated, the central processing unit changes the flag into a state indicating an incomplete save state. When the computer system must be stopped, the central processing unit saves data, of the data stored in the main memory, only from a storage area for which the flag indicates an incomplete save state into the auxiliary memory, thereby shortening the time required for save processing.

Abstract: A cache control maintains a history table SETLAT for the prediction of line entry (i.e., set member) within a congruence class for cache accessing. For a given cache access, a SETLAT entry can be selected based on the requesting logical address bits directly. The selection of a SETLAT entry may also be based on the hashing of such logical address bits together with other information in order to achieve sufficient randomization. A similar hashing history table may be devised to predict virtual address translation information with high accuracy. Such prediction mechanisms not only allow efficient implementation of the cache access path but also offer the opportunity of achieving multiple accesses per cycle.The proposed prediction method also provides a generic approach to efficient implementations for various directory based table accesses.

Abstract: A memory controller for controlling access to a memory includes a circuit for generating memory signals, including address and control signals, for accessing a memory in response to a physical address, and a circuit for programming the timing of the memory signals in response to predetermined timing control information which defines the timing requirements of the memory. The circuit for programming the timing of the memory preferably includes a register for storing timing control bits and selectors responsive to the timing control bits for selecting timing control parameters from a group of predetermined timing control parameters. The circuit for programming the timing preferably further includes a circuit responsive to each timing control parameter and to a selected memory signal for generating a timing control signal. The timing control signal controls the timing of one of the memory signals.

Abstract: The disk drive array data storage subsystem maps between virtual and physical data storage devices and schedules the writing of data to these devices. The data storage subsystem functions as a conventional large form factor disk drive memory, using an array of redundancy groups, each containing N+M disk drives. This system copies data records by simply creating a duplicate data record pointer in a virtual track directory to reference the original data record. This enables the host processor to access the data record via two virtual addresses while only a single physical copy of the data record resides in the data storage subsystem.

Abstract: A process and apparatus for shadowing memory uses a single memory chip which is addressable into an address field which is smaller than the memory chip. A program having a main control portion is programmed into a main memory area of the memory chip and is directly connected to a main address space of the address field. The program also includes a plurality of secondary program portions which can be used one at a time with the main control portion of the program. Each of the secondary program portions is stored in a separate secondary and shadowed memory area of the memory chip. A secondary address space of the address field which is large enough to accommodate only one secondary memory area at a time, is controlled so as to be latched to only one secondary memory area at a time. Latching is achieved through higher bits of address locations in a selected portion of the address field.

Abstract: A data processing system (10) having a dual purpose memory (14) comprising multiple cache sets. Each cache set can be individually configured as either a cache set or as a static random access memory (SRAM) bank. Based upon the configuration of the set, the tag store array (58) is used for storage of actual data, in the SRAM mode, or for storage of a set of tag entries in the cache mode. A module configuration register (40) specifies the mode of each set/bank. A set of base address registers (41-44) define the upper bits of a base address of SRAM banks. In SRAM mode, comparison logic (66) compares a tag field of the requested address (50) to the base address to determine an access hit. The least significant bit of the address, tag field is used to select either the tag store array (58) or the line array (60) for the requested address data read or write.

Abstract: A central processing unit (CPU) 10 comprises an external control memory for storing microinstructions which correspond to macroinstructions read from a system memory. The microinstructions are 56 bits in length and are read in 28-bit segments. CPU 10 also comprises an internal memory management unit (MMU) 18 which comprises a plurality of address translation entry (ATE) registers four of which are permanent and sixteen of which are temporary in that the storage of a new translation entry occurs in a least recently used temporary translation entry register. CPU 10 also comprises a plurality of status register bits, some of which are settable only by predefined microinstructions. All of the status register bits are branchable. CPU 10 further comprises a condition code register the state of which may be determined by input signal pins. CPU 10 also comprises address generation logic which may generate a 24, 31 or 32 bit address upon a 32-bit address bus.

Abstract: A virtual storage management method in a multi-processor system in which individual processors share an external storage is shown. Data of the virtual storage is stored in the shared external storage, and a page table for managing the virtual storage of each processor is also stored in the shared external storage. By exclusively controlling an access to that page table, the virtual storage can be managed.