Abstract: The present invention relates to a sensor including a core-shell nanostructure, and more particularly, to a sensor including: a base material; a sensing part including a core-shell nanostructure that has a core including a first metal oxide and a shell including a second metal oxide formed on the core; and two electrode layers spaced from each other on the sensing part.

Abstract: An article may include a structure including a patterned metal on a surface of a substrate, the patterned metal including metal features separated by gaps of an average dimension of less than about 1000 nm. A porous low dielectric constant material having a dielectric value of less than about 2.7 substantially occupies all gaps. An interface between the metal features and the porous low dielectric constant material may include less than about 0.1% by volume of voids. A method may include depositing a filling material including a silicon-based resin having a molecular weight of less than about 30,000 Da and a porogen having a molecular weight greater than about 400 Da onto a structure comprising a patterned metal. The deposited filling material may be subjected to a first thermal treatment to substantially fill all gaps, and subjected to a second thermal treatment and a UV radiation treatment.

Abstract: A method of forming a transistor can include forming a gate mask on a substrate having a vertical location aligned with that of a transistor control gate; implanting first conductivity type dopants with the gate mask as an implant mask to form a first shallow halo region; implanting first conductivity type dopants with at least the gate mask as an implant mask to form a first deep halo region having a peak dopant concentration profile at a greater substrate depth than the first shallow halo region; forming an epitaxial layer on top of the substrate; forming a first control gate structure on the epitaxial layer; and forming a first source or drain region, of a second conductivity type, in at least the epitaxial layer to a side of the first control gate, and over the first shallow halo region and the first deep halo region.

Abstract: A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the substrate, a N-doped drift region being formed in said epitaxial layer; a P-doped base layer of said III-N material, formed on top of at least a portion of the drift region; a N-doped source region of said III-N material; formed on at least a portion of the base layer; and a gate trench having at least one vertical wall extending along at least a portion of the source region and at least a portion of the base layer; wherein at least a portion of the P-doped base layer along the gate trench is a layer of said P-doped III-N material that additionally comprises a percentage of aluminum.

Abstract: A semiconductor structure comprising a layer of a III-N material and at least a portion of said layer being covered by a passivation layer, wherein the passivation layer comprises a first layer of SiN formed on said at least a portion of said III-N material layer and a second layer of SiN formed on said first layer of SiN; the first SiN layer having a first thickness and generating tensile stress in the structure and the second SiN layer having a second thickness and generating compressive stress in the structure.

Abstract: A semiconductor device includes a substrate, a channel layer, a spacer layer, a barrier layer, and an oxidized cap layer. The channel layer is disposed on or above the substrate. The spacer layer is disposed on the channel layer. The barrier layer is disposed on the spacer layer. The oxidized cap layer is disposed on the barrier layer. The oxidized cap layer is made of oxynitride.

Abstract: After sequentially forming a first multilayer structure comprising a first set of semiconductor layers suitable for formation of a photodetector, an etch stop layer and a second multilayer structure comprising a second set of semiconductor layers suitable for formation of a light source over a substrate, the second multilayer structure is patterned to form a light source in a first region of the substrate. A first trench is then formed extending through the etch stop layer and the first multilayer structure to separate the first multilayer structure into a first part located underneath the light source and a second part that defines a photodetector located in a second region of the substrate. Next, an interlevel dielectric (ILD) layer is formed over the light source, the photodetector and the substrate. A second trench that defines a microfluidic channel is formed within the ILD layer and above the photodetector.

Abstract: A Single-Photon Avalanche Diode (SPAD) device an active region configured to detect incident radiation, a first radiation blocking ring surrounding the active region, and a radiation blocking cover configured to shield part of the active region from the incident radiation. The radiation blocking cover is configured to define a second radiation blocking ring vertically spaced apart from the first radiation blocking ring. The SPAD device may include radiation blocking vias extending between the first and second radiation blocking rings.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas. The gate electrode is electrically insulated from the neighboring semiconductor mesas by respective dielectric layers. A respective pillar on each of the neighboring semiconductor mesas is formed, leaving an opening between the pillars above the trench. Dielectric contact spacers are formed in the opening along respective pillar side walls to narrow the opening above the gate electrode. A conductor is formed, having an interface with the gate electrode. The interface extends along an extension of the gate electrode, and the conductor has a conductivity greater than the conductivity of the gate electrode.

Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.

Abstract: A change in electrical characteristics in a semiconductor device including an oxide semiconductor film is inhibited, and the reliability is improved. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, a first metal oxide film over the second insulating film, and a second metal oxide film over the first metal oxide film. The first metal oxide film contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film. The second metal oxide film includes a region where the second metal oxide film and the first metal oxide film are mixed.

Abstract: To provide a semiconductor device having a structure with which the device can be easily manufactured even if the size is decreased and which can suppress a decrease in electrical characteristics caused by the decrease in the size, and a manufacturing method thereof. A source electrode layer and a drain electrode layer are formed on an upper surface of an oxide semiconductor layer. A side surface of the oxide semiconductor layer and a side surface of the source electrode layer are provided on the same surface and are electrically connected to a first wiring. Further, a side surface of the oxide semiconductor layer and a side surface of the drain electrode layer are provided on the same surface and are electrically connected to a second wiring.

Abstract: Photovoltaic cells having copper contacts can be made by using copper nanoparticles during their fabrication. Such photovoltaic cells can include a copper-based current collector located on a semiconductor substrate having an n-doped region and a p-doped region. The semiconductor substrate is configured for receipt of electromagnetic radiation and generation of an electrical current therefrom. The copper-based current collector includes an electrically conductive diffusion barrier disposed on the semiconductor substrate and a copper contact disposed on the electrically conductive diffusion barrier. The copper contact is formed from copper nanoparticles that have been at least partially fused together. The electrically conductive diffusion barrier limits the passage of copper therethrough.

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus that are capable of increasing a work function of a film to be formed, in comparison with a related art. The method comprises: (a) supplying a metal-containing gas simultaneously with one selected from the group consisting of an oxygen-containing gas, a halogen-containing gas and combinations thereof into a processing chamber accommodating the substrate; and (b) supplying a nitrogen-containing gas with one of the oxygen-containing gas, the halogen-containing gas and the combinations thereof into the processing chamber.

Abstract: A lead frame has a metal base, a silver-plated layer, and a silver oxide layer. The silver-plated layer is formed between the metal base and the silver oxide layer. The silver oxide layer has a polar outer surface and a thickness of equal to or more than 1.3 nanometers. The silver oxide layer is beneficial to increase the adhesive strength between the lead frame and the molding compound and avoid delamination of the molding compound from the lead frame, so the lead frame of the present invention can pass a more severe moisture sensitivity level when exposed to the environment.

Abstract: A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure.

Abstract: A SiO2 layer is formed at a middle of a Si pillar. An opening is formed in a gate insulating layer and a gate conductor layer in a peripheral portion that includes a side surface of the SiO2 layer. Two stacks of layers, each stack being constituted by a Ni layer, a poly-Si layer containing a donor or acceptor impurity atom, and a SiO2 layer, are formed in a peripheral portion of the opening, and heat treatment is performed to silicidate the poly-Si layers into NiSi layers. The NiSi layers protrude and come into contact with the side surface of the Si pillar by silicidation, and a donor or acceptor impurity atom diffuses from the NiSi layers into the Si pillar. Thus an N+ region and a P+ region serving as a source and a drain of surrounding gate MOS transistors are respectively formed above and under the SiO2 layer.

Abstract: A pixel of a complementary metal-oxide-semiconductor (CMOS) image sensor includes a semiconductor substrate having a first surface and a third surface formed by removing part of the semiconductor substrate from a second surface, an active region which is formed between the first surface and the third surface and which contains a photoelectric conversion element generating charges in response to light incident on the substrate at the third surface, and a trench-type isolation region formed from either of the first and third surfaces to isolate the active region from an adjacent active region. The trench-type isolation region is filled with first material in a process that leaves a void in the material, the void is filled or partially filled with second material, and then a layer of third material is formed over the resulting structure composed of the first and second materials.