Patents Examined by Reginald G. Bragdon
  • Patent number: 11687268
    Abstract: A storage system includes a first storage device that includes a first memory and a first processor coupled to the first memory; and a second storage device that includes a second memory and a second processor coupled to the second memory, wherein the first processor is configured to: when migrating data in object units, generate dummy data that corresponds to the data instead of the data in object units, and transmit management information used to manage an object and the dummy data to the second storage device, and the second processor is configured to: store the management information in a storage unit in association with the object, and discard the dummy data.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: June 27, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Taketoshi Yoshida
  • Patent number: 11681459
    Abstract: A method, computer program product, and computer system for submitting, by a computing device, a write for a write-request equal to a size of valid data in a segment. The write-request may be decomposed into RAID elements and corresponding parity stripe elements. Parity for RAID stripes may be calculated using only valid RAID elements of the RAID elements. A write for all the valid RAID elements and the corresponding parity stripe elements may be issued. An unmap command may be issued to at least a portion of the segment that is invalid.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: June 20, 2023
    Assignee: EMC IP Holding Company, LLC
    Inventors: Vamsi K. Vankamamidi, Amitai Alkalay, Shuyu Lee
  • Patent number: 11675615
    Abstract: Zero copy message reception for guests is disclosed. For example, a host has a memory, a device with access to device memory addresses, a processor, and a supervisor. An application with access to application memory addresses (AMA) executes on the host. An AMA is mapped to a page table entry (PTE). The application shares access to a first page of memory addressed by the AMA with the device to store data received by the device for the first application, where the first page is mapped as a device memory address of the plurality of device memory addresses. The application later sends a request to disconnect from the device. The supervisor is configured to copy contents of the first page to a second page in the memory after receiving the request to disconnect, and then update the PTE to address the second page instead of the first page.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: June 13, 2023
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 11675540
    Abstract: A system includes a storage device and a computational storage processor. The storage device includes media. The computational storage processor is configured to, after issuance of a single command from a host device, receive data corresponding to the command, process the data as the data is received using a filter program and provide results data from the processed data.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: June 13, 2023
    Assignee: Seagate Technology LLC
    Inventor: Marc Timothy Jones
  • Patent number: 11669269
    Abstract: According to one embodiment, a memory system stores write data received from a host to a shared write buffer for write destination blocks, acquires first write data for plural pages from the shared write buffer, and writes the first write data to a first write destination block by a first-step write operation. When receiving write data from the host in a state in which an empty region does not exist in the shared write buffer, the memory system discards write data in the shared write buffer in which the first-step write operation has been finished. In a case where the first write data do not exist in the shared write buffer when a second-step write operation of the first write data is to be executed, the memory system transmits a request to acquire the first write data to the host.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: June 6, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11669246
    Abstract: Method and system are provided for storage allocation enhancement of microservices. A method carried out at a microservice orchestrator, includes: categorizing a microservice container, wherein the categorization defines a predicted storage behavior of the microservice container input/output operations; and providing the categorization in association with the microservice container input/output operations to a storage system for use in storage allocation of the input/output operations. A method at a storage controller includes: receiving microservice container input/output operations with an associated categorization, wherein the categorization defines a predicted storage behavior of the microservice container input/output operations; and using the associated categorization for optimizing storage allocation for the input/output operations and/or optimizing garbage collection performance.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 6, 2023
    Assignee: International Business Machines Corporation
    Inventors: Miles Mulholland, Lee Jason Sanders, Adam Michael Farley, Keira Louise Hopkins, Jason Hughes
  • Patent number: 11662940
    Abstract: A data storage device includes a memory device and a memory controller. The memory controller configures a first memory block which is a TLC memory blocks as a data buffer, and accordingly configures a plurality of second memory blocks which are SLC memory blocks. The memory controller uses the first memory block to receive data and accordingly store same data in the second memory blocks as backup data. When an amount of available memory space of the first memory block is smaller than or equal to a predetermined amount, the memory controller determines whether any error has occurred in the data stored in the first memory block. When there is any error occurred in the data stored in the first memory block, the memory controller configures a third memory block and move the backup data stored in the second memory block to the third memory block.
    Type: Grant
    Filed: October 25, 2020
    Date of Patent: May 30, 2023
    Assignee: Silicon Motion, Inc.
    Inventor: Tzu-Yi Yang
  • Patent number: 11650752
    Abstract: A computing system includes: a memory device including a memory cells; a memory controller configured to control the memory device; and a host configured to detect an occurrence of an error in a first memory cell of the memory device while performing an operation corresponding to a workload and transmit, to the memory controller, a target address corresponding to the first memory cell and a request for a test operation on adjacent memory cells that are adjacent to the first memory cell. The memory controller controls the memory device to perform the test operation on the adjacent memory cells by using at least one of a Built-In Self-Test (BIST) engine or a scrub engine based on the target address and generate memory error information including information associated with a second memory cell in which the error occurs, the second memory cell being one of the adjacent memory cells. The host controls an access to the second memory cell based on the memory error information.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: May 16, 2023
    Assignee: SK hynix Inc.
    Inventors: Nam Young Ahn, Yong Tag Song
  • Patent number: 11645011
    Abstract: A computational storage device includes a non-volatile memory (NVM) device; and a storage controller configured to control the NVM device. The storage controller includes: a computation processor configured to execute an internal application to generate an internal command; a host interface circuit configured to receive a host command from an external host device, to receive the internal command from the computation processor, and to individually process the received host command and the received internal command; a flash translation layer (FTL) configured to perform an address mapping operation based on a result of the processing of the host interface circuit; and a memory interface circuit configured to control the NVM device based on the address mapping operation of the FTL.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwang Lee, Wan Heo
  • Patent number: 11640270
    Abstract: Firmware instruction(s) are selected from a plurality of firmware instructions based at least in part on: (1) a conditions table that includes one or more conditions for handling the plurality of firmware instructions and (2) state information. It is determined how to handle the one or more selected firmware instructions based at least in part on: (1) the conditions table and (2) the state information. In the event the determined handling is to perform the selected firmware instructions, an instruction sequence is obtained, from a sequencing table that includes one or more instruction sequences associated with a storage media device, based at least in part on the one or more selected firmware instructions. In the event the determined handling is to perform the one or more selected firmware instructions, the obtained instruction sequence is output to the storage media device.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: May 2, 2023
    Inventors: Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Wanqiang Zhang
  • Patent number: 11640251
    Abstract: The present disclosure generally relates to data storage devices, such as solid state drives, and effective power management of the data storage device. The data storage device includes a controller, where the controller is configured to predict when a host device will send a command to enter a low power state, prepare the data storage device to enter the low power state, and receive a command to enter the low power state after the predicting and preparing. If the data storage device is idled for greater than a threshold value, then the data storage device prepares to transition to a low power state but will wait to enter the lower power state until receiving a request from a host device.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 2, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Judah Gamliel Hahn, Ariel Navon
  • Patent number: 11636045
    Abstract: Translating virtual addresses to second addresses by a memory controller local to one or more memory devices, wherein the memory controller is not local to a processor, a buffer for storing a plurality of Page Table Entries, or a Page Walk Cache for storing a plurality of page directory entries, the method including by the memory controller: receiving a page directory base and a plurality of memory offsets from the processor; reading a first level page directory entry using the page directory base and a first level memory offset; combining the second level offset and the first level page directory entry; reading a second level page directory entry using the first level page directory entry and the second level memory offset; sending to the processor the first level page directory entry or the second level page directory entry; and sending a page table entry to the processor.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: April 25, 2023
    Assignee: International Business Machines Corporation
    Inventors: Mohit Karve, Brian W. Thompto
  • Patent number: 11630596
    Abstract: Managed drives of a storage node with different size drives in a fixed arithmetic relationship are organized into clusters of same size drives. Every drive is configured to have M*G same-size partitions, where M is a positive integer variable defined by the arithmetic relationship and G is the RAID group size. The storage capacity of all drives can be viewed as matrices of G+1 rows and M*G columns, and each matrix is composed of submatrices of G+1 rows and G columns. Diagonal spare partitions are allocated and distributed in the same pattern over groups of G columns of all matrices, for increasing partition index values. Members of RAID groups are vertically distributed such that the members of a given RAID group reside in a single partition index of a single cluster. When a drive fails, protection group members of the failed drive are rebuilt in order on spare partitions characterized by lowest partition indices for increasing drive numbers across multiple clusters.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: April 18, 2023
    Assignee: Dell Products L.P.
    Inventors: Kuolin Hua, Kunxiu Gao
  • Patent number: 11625184
    Abstract: Embodiments are disclosed for a method. The method includes migrating a file to a newer tape. The file is previously recalled by a linear tape file system (LTFS) from an older tape. The method also includes updating a stub for the file with metadata describing the newer tape, the older tape, and the file. Further, the method includes recalling the file using a tape selected from a plurality of potential tapes identified by the metadata.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: April 11, 2023
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Tsuyoshi Miyamura, Hiroshi Itagaki, Atsushi Abe, Noriko Yamamoto, Shinsuke Mitsuma
  • Patent number: 11620085
    Abstract: A processing device, operatively coupled with a memory device, performs operations including receiving a write request from a host system at a first time, the write request identifying first data to be stored in a segment of the memory device, determining whether a pre-read voltage level of the write request satisfies a pre-read voltage level criterion pertaining to a write-to-write time interval for the segment, wherein the write-to-write time interval is defined by the first time and a second time corresponding to a last time at which the segment was written, and responsive to determining that the pre-read voltage level satisfies the pre-read voltage level criterion pertaining to the write-to-write time interval, performing a pre-read operation on the segment using the pre-read voltage level to determine second data currently stored in the segment.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: April 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Patent number: 11615033
    Abstract: Systems, apparatuses, and methods for performing efficient translation lookaside buffer (TLB) invalidation operations for splintered pages are described. When a TLB receives an invalidation request for a specified translation context, and the invalidation request maps to an entry with a relatively large page size, the TLB does not know if there are multiple translation entries stored in the TLB for smaller splintered pages of the relatively large page. The TLB tracks whether or not splintered pages for each translation context have been installed. If a TLB invalidate (TLBI) request is received, and splintered pages have not been installed, no searches are needed for splintered pages. To refresh the sticky bits, whenever a full TLB search is performed, the TLB rescans for splintered pages for other translation contexts. If no splintered pages are found, the sticky bit can be cleared and the number of full TLBI searches is reduced.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: March 28, 2023
    Assignee: Apple Inc.
    Inventors: John D. Pape, Brian R. Mestan, Peter G. Soderquist
  • Patent number: 11604595
    Abstract: A method for managing composed information handling systems includes receiving, by a system control processor, a mirroring policy from a system control processor manager, receiving an application write request from a first application instance, based on the application write request and the mirroring policy: initiating servicing of the application write request by a first composed information handling system, initiating servicing of an SCP write request by a second composed information handling system, wherein the SCP write request is based on the application write request, receiving a SCP response from the SCP write request from a second system control processor, wherein a second composed information handling system comprises the second system control processor and is executing a second application instance of the cluster application, and sending a write response to the first application instance, wherein the write response is based, at least in part, on the SCP response.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: March 14, 2023
    Assignee: Dell Products L.P.
    Inventors: Yossef Saad, William Price Dawkins
  • Patent number: 11593483
    Abstract: Memory allocation techniques may provide improved security and performance. A method may comprise mapping a block of memory, dividing the block of memory into a plurality of heaps, dividing each heap into a plurality of sub-heaps, wherein each sub-heap is associated with one thread of software executing in the computer system, dividing each sub-heap into a plurality of bags, wherein each bag is associated with one size class of objects, creating an allocation buffer and a deallocation buffer for each bag, storing a plurality of objects in at least some of the bags, wherein each object is stored in a bag having size class corresponding to a size of the object, storing in the allocation buffer of each bag information relating to available objects stored in that bag, and storing in the deallocation buffer of each bag information relating to freed objects that were stored in that bag.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: February 28, 2023
    Assignee: The Board of Regents of The University of Texas System
    Inventors: Tongping Liu, Sam Albert Silvestro, Hongyu Liu, Tianyi Liu
  • Patent number: 11593031
    Abstract: An electronic device may include a host device and a storage device which are connected in a universal flash storage standard, wherein the host device may include processing circuitry configured to process a submission queue (SQ) and a completion queue (CQ), wherein the SQ is a processing standby line of a command, and the CQ is a processing standby line of a response received from the storage device, transmit the command to the storage device, store a host command credit in a host command register, the host command credit indicating an estimated command accommodation limit of the storage device, store the response in a response slot, and store a host response credit in a host command register, the host command credit indicating a limit of the response slot.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: February 28, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myungsub Shin, Sungho Seo, Seongyong Jang, Haesung Jung
  • Patent number: 11586371
    Abstract: A method of populating page tables of an executing workload during migration of the executing workload from a source host to a destination host includes the steps of: before resuming the workload at the destination host, populating the page tables of the workload at the destination host, wherein the populating comprises inserting mappings from virtual addresses of the workload to physical addresses of system memory of the destination host; and upon completion of populating the page tables, resuming the workload at the destination host.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 21, 2023
    Assignee: VMware, Inc.
    Inventors: Yury Baskakov, Ying Yu, Anurekh Saxena, Arunachalam Ramanathan, Frederick Joseph Jacobs, Giritharan Rashiyamany