Patents Examined by Rehana Perreen Krick
  • Patent number: 5687389
    Abstract: A host interface uses a state machine to control multiple sector transfers between a host computer and a physical storage medium, so that the idle time between sector transfers is minimized and not a function of the local microprocessor. A write sector counter is provided to keep track of the largest segment in a buffer memory so that demands for the local microprocessor is minimized. In addition, start counters pointing at the next sector in the buffer memory are provided to shorten response time in a read cache. BUSY and IRQ timers are provided to accommodate various implementations of BIOS's which may inadvertently clear a host interrupt to lead to a failure condition.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: November 11, 1997
    Assignee: Adaptec, Inc.
    Inventor: John S. Packer
  • Patent number: 5659796
    Abstract: A method optimizes routing in a multiprocessor computer system by defining two types of virtual channels having virtual channel buffers for storing messages communicated between processing element nodes in the multiprocessor computer system. A dateline is associated to each type of virtual channel, and messages are restrained from crossing a dateline on its associated type of virtual channel to avoid deadlock. A cost function is defined which is correlated to imbalances in the utilization of the two types of virtual channels. The unrestrained messages are allocated between the two types of virtual channels to minimize the cost function by defining an initial virtual channel allocation, randomly modifying the virtual channel allocation, and accepting the random modification if the modification decreases the cost function, else accepting the modification based on a probability that slowly decreases during the allocating step.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: August 19, 1997
    Assignee: Cray Research, Inc.
    Inventors: Gregory M. Thorson, Steven L. Scott