Abstract: Single-instruction multiple-data is a new class of integrated video signal processors especially suited for real-time processing of two-dimensional images. The single-instruction, multiple-data architecture is adopted to exploit the high degree of parallelism inherent in many video signal processing algorithms. Features have been added to the architecture which support conditional execution and sequencing--an inherent limitation of traditional single-instruction multiple-data machines. A separate transfer engine offloads transaction processing from the execution core, allowing balancing of input/output and compute resources--a critical factor in optimizing performance for video processing. These features, coupled with a scalable architecture allow a united programming model and application driven performance.

Abstract: A method and system for interconnecting software components. In a preferred embodiment, the present invention instantiates an event object. The event object includes message information describing the message and a dispatching member function for invoking a member function of a target object passing the message information. A message is passed by invoking the dispatching member function of the event object passing an identifier to a target object and an identifier of a member function of the target object. The dispatching member function invokes the identified member function of the identified target object passing the event information as an actual parameter. The event object is preferably of a derived class that inherits a base class. The base class provides common event behavior, while the derived class provides behavior specific to a type of message.

Abstract: Disclosed is a multiprocessor system made up of several processing nodes linked by a time division multiplexed (TDM) bus to form a synchronous system. According to one embodiment, each processing node includes a digital signal processing (DSP) element, a dual port memory element and a memory control element in an integrated structure. Each memory element is segmented into four quarters. The first two are for read operations by the DSP element and write operations by the bus. However, the DSP element and the bus can only access any given segment during opposite phases of a frame clock signal. Additionally, each node is assigned an exclusive identification code whereby each node can post data to a memory element of another node.According to another embodiment, the various elements of each node are combined in various integrated structures.

Abstract: In a printing-information processing method and apparatus, print jobs input from outside are sequentially stored in a reception buffer, analysis information of each of the stored print jobs is stored in a page buffer in parallel with the reception of the print jobs, and page data obtained from the stored analysis information is sequentially stored in the frame buffer. At that time, data for assigning deletion of a job input from the outside is also stored. Hence, an assigned print job stored in the reception buffer, or analysis information or page data stored in the page buffer or the frame buffer, respectively, corresponding to the assigned print job is deleted by analyzing the stored data for assigning deletion of a print job.

Abstract: Disclosed is an exclusive control method in an I/O subsystem having an exclusive controller which is provided with an exclusive control table and which permits a host interface to use the I/O device when the I/O device is not used by any other host interface while prohibiting the use when another host interface is using the I/O device.

Abstract: Disclosed is a support architecture that facilitates use of display device drivers containing a minimum of hardware-specific software code. A driver need support only a relatively few common functions, which act as building blocks for the larger, more complex operations typically requested by graphics engines. In order to mediate between the limited-instruction-set device driver and the various higher-level graphics engines, the invention includes a series of translation modules that simplify engine-originated instructions into simpler graphic components. A video manager supervises routing of instructions to the specific drivers they designate, and serializes access to hardware components so that graphic commands execute atomically (i.e., without interruption).

Abstract: In a communication network having a set of hosts and switch based label swapping communication nodes, each node has a control processor that is also a host that sends and receives messages via the switching apparatus in its associated node. At least one of the hosts includes a distribution tree set up procedure. That procedure stores source and destination data designating a set of source hosts and a set of destination hosts in the communication network, and defines a distribution tree of virtual connections. The designated source hosts and destination hosts may include the control processors of some or all the network nodes. The defined virtual connections include a virtual connection from each designated source host to all of the designated destination hosts, and message labels for all messages sent by the source hosts to be routed to the destination nodes.

Abstract: A display management architecture detects changes in a display environment and notifies software programs, such as the operating system and applications programs, of the changes to enable them to adjust accordingly. The display management system comprises one part of the computer's operating system, and includes a display manager that provides communication channels between the operating system, other software programs, display drivers and video drivers. The display manager receives information from the drivers regarding the display capabilities of associated display devices, and provides reconfiguration services to other software within the computer. When a change in the display environment occurs, the display manager notifies the software programs of the changes, to enable them to dynamically update or reconfigure the displayed information accordingly. If a program is not able to respond to such a notification, the display manager repositions displayed objects in accordance with the new display environment.

Abstract: Communication control equipment for connecting a computer system to a network and supporting the computer system to set a plurality of connections on the network and perform parallel communication between computers.

Abstract: A hybrid decoding module which resides on the computer system's high speed memory bus. The computer system incorporating the hybrid decoding module scheme is capable of having centrally decoded resources on the memory bus as well as resources capable of decoding memory bus addresses directly. During system initialization, or after a hard reset, the decoding logic polls each of the resources on the memory bus to determine whether the resource is a centrally decoded resource or a distributed decode resource. A table is maintained for all centrally decoded resources such that when addresses are put out by the processor during run-time, the decoding logic is capable of directing control to the centrally decoded resource. Another aspect of the present invention is implemented during the initialization of the system. When resources are polled by the decoding logic, they are also provided with an identifier which identifies the last available I/O space slot.

Abstract: An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance wit

Abstract: An automatic identification system includes a reader device, such as a bar code wand, laser bar code reader, CCD, m or combination of reader devices, such as magnetic stripe reader, badge slot reader, or touch memory pen. A slave interface is provided for transferring raw reader signals from the reader device to a communication port of a personal computer. The invention provides a hardware and software system which permits interfacing of multiple reading devices and device types into a single port, and which provides efficient power management.

Abstract: A method and system for interconnecting software components. In a preferred embodiment, the present invention instantiates an event object. The event object includes message information describing the message and a dispatching member function for invoking a member function of a target object passing the message information. A message is passed by invoking the dispatching member function of the event object passing an identifier to a target object and an identifier of a member function of the target object. The dispatching member function invokes the identified member function of the identified target object passing the event information as an actual parameter. The event object is preferably of a derived class that inherits a base class. The base class provides common event behavior, while the derived class provides behavior specific to a type of message.

Abstract: The present invention is a computer-implemented method, memory, and computer system for directing a computer system to incrementally archive primary storage to archive storage based on partitions. The primary storage is divided into a plurality of partitions, where at least one the partitions contains information. The method includes the steps of receiving an incremental archive request from user controls and, in response, storing in the archive storage a copy of the information in each partition that has been modified since the last archive, if any.

Abstract: An arithmetic logic unit (230) may be divided into a plurality of independent sections (301, 302, 303, 340). A bit zero of carry status signal corresponding to each section that is stored in a flags register (211), which preferably includes more bits than the maximum number of sections of the arithmetic logic unit (230). New status signals may overwrite the previous status signals or rotate the stored bits and store the new status signals. A status register (210) stores a size indicator that determines the a number of sections of the arithmetic logic unit (230). A status detector has a zero detector (321, 322, 323, 324) for each elementary section (301, 302, 303, 304) of the arithmetic logic unit (230). When there are fewer than the maximum number of sections, these zero signals are ANDed (331, 332, 341). A multiplexer couples the carry-out of an elementary (311, 312, 313, 314) to the carry-in of an adjacent elementary section (301, 302, 303, 304) or not depending on the selected number of sections.

Abstract: A dataframe filter is provided a local area network bridge to monitor the dataframes transmitted on one network to determine those dataframes destined to be communicated to another network by the network bridge. The filter receives and examines the destination address of each dataframe communicated on the one filter and, searching through a database maintained by the filter, determine whether the destination address is located on the second network and, if so, signals the bridge to copy the dataframe to the second network.

Abstract: A pair of data processing systems, each of the data processing system having a host central processor and an associated controller including memory, both of the data processing systems to be cooperatively associated with a number of disk drive memory units, each of the disk drive memory unit coupled to both said controllers. Either one of the host central processors can appropriate any one of the disk drive memory units as a selected disk drive memory unit by propagating path-control-data to the memory in both of the controllers and in the selected disk drive memory unit.

Abstract: A multi-node data processing system implements a method that assures that plural messages are enabled "fair" access to a data stream. Each node includes apparatus for controlling message transmissions and/or receptions from another node over a communication network. The method comprises the steps of: transmitting a routing message from a first destination node to a source node, the routing message signalling a readiness of the destination node to receive a data message; transmitting a first data message to the first destination node from the source node in response to the ready message; transmitting a conditional disconnect message from the first destination node to the source node upon receipt of a predetermined amount (i.e. a "slice") of the first data message.

Abstract: The invention concerns using multiple computers to hold a conference. Under the invention, an application program can run on a single computer, yet remote participants can issue commands to the program. Remote participants can watch the program operate, because the invention replicates the display window of the running program onto the displays of the remote computers. Any participant can make annotations on the participant's own computer display. The invention copies the annotations to the displays of the other participants.

Abstract: A filter module allows controlling network security by specifying security rules for traffic in the network and accepting or dropping communication packets according to these security rules. A set of security rules are defined in a high level form and are translated into a packet filter code. The packet filter code is loaded into packet filter modules located in strategic points in the network. Each packet transmitted or received at these locations is inspected by performing the instructions in the packet filter code. The result of the packet filter code operation decides whether to accept (pass) or reject (drop) the packet, disallowing the communication attempt.