Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

Abstract: Structures and methods for flash memory transistors are formed with self-aligned drain/source contacts. The flash transistors are formed with a plurality of gate layers. An etch resistant layer(s) are deposited on top of the gate layers in the memory array transistors and on the gate layers of peripheral transistors. An additional oxide layer/spacer may be formed on the etch resistant layer to control the resulting transistor junction configuration. As a result within the same process various transistors may be formed satisfying various requirements. Contact holes to the drain and source regions of the memory and peripheral transistors are then formed. The etch resistant layer prevents the contact etchants from completely etching away the protective etch resistant layer surrounding the gate layers. The spacing between the drain/source contacts and the gate layers can be greatly reduced increasing the density of the memory array transistors and reducing chip size.

Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Abstract: A lithography method for plating sub-100 nm narrow trenches, including providing a thin undercoat dissolution layer intermediate a seed layer and a resist layer, wherein the undercoat dissolution layer is relatively completely cleared off the seed layer by the developer solution such that the sides of the narrow trench will be generally vertical, particularly at the base of the narrow trench, thus facilitating plating the narrow trench with a high magnetic moment material.

Abstract: A system for fabricating a compound semiconductor device includes a gas treatment apparatus that performs a hydrogen chloride gas etching on a compound semiconductor substrate, a radical treatment apparatus that performs a radical hydrotreatment on the substrate, a semiconductor film forming apparatus that forms a compound semiconductor film on the treated substrate, a conductive film forming apparatus that forms a conductive film on the substrate, and an ultrahigh vacuum transfer path that connects together the several apparatuses so that the substrate being processed can be transferred through the transfer path from apparatus to apparatus under a continuously maintained ultrahigh vacuum environment. Some of the apparatuses can overlap or share functions with one another.

Abstract: As shown in FIG. 1(a), a gate oxide film 12 is formed on an Si substrate 11. A polysilicon layer 13 is formed thereon. A natural oxide film 14 having an arbitrary thickness is formed on the polysilicon layer 13 after phosphorus is made to diffuse into the polysilicon layer 13 and before a resist layer is coated. Thus, as shown in FIG. 1(b), the natural oxide film 14 present on the polysilicon layer 13 is removed by DHF cleaning (cleaning with dilute HF). Thereafter, a resist layer 15 is coated onto the polysilicon layer 13, and is patterned. A polysilicon gate electrode G is formed by dry-etching using the resist layer 15 as a mask.

Abstract: A method for ionization film formation to form a deposited film by ionizing vaporized particles with an ionization mechanism of the hot-cathode system and injecting the ionized particles into a substrate is provided. The method includes the step of introducing He gas inside the ionization mechanism.

Abstract: The present invention provides a semiconductor manufacturing apparatus capable of shortening TAT by completing a plurality of processes including plating, annealing, and CMP-in-twice or the like in copper wiring process in a single manufacturing apparatus, and is also capable of suppressing costs for consumable materials by replacing the CMP step with other step. The apparatus of the present invention comprises an electrolytic plating chamber (11) for performing electrolytic plating of a substrate (91), an electrolytic polishing chamber (21) for performing electrolytic polishing of the substrate, and a conveying chamber (81) having installed therein a conveying instrument (83) responsible for loading/unloading of the substrate to or from the electrolytic plating chamber, and to or from he electrolytic polishing chamber, and is connected respectively to the electrolytic plating chamber and the electrolytic polishing chamber.

Abstract: A magnetic memory array comprises a plurality of magnetic memory cells, a magnetic shielding disposed adjacent to at least one of the magnetic memory cells to reduce magnetic interference with respect to another of the magnetic memory cells, and an insulator disposed as to separate at least a portion of the magnetic shielding from the at least one magnetic memory cell. The magnetic shielding may be a magnetic shield layer, patterned magnetic shield materials, and/or magnetic particles embedded in the insulator.

Abstract: A method of forming electrically conductive elements on a base layer of an electronic substrate without the use of solder mask. A layer of electrically conductive material is deposited on the base layer, and a first layer of photo imageable ink is applied over the electrically conductive material layer. The first layer of photo imageable ink is patterned to expose portions of the electrically conductive material layer, which are then etched to resolve traces in the electrically conductive material layer. The first layer of photo imageable ink is removed, and a second layer of photo imageable ink is applied over the traces and channels between the traces. The second layer of photo imageable ink is then patterned to expose the traces, and a third layer of photo imageable ink is applied over the traces and the second layer of photo imageable ink. The third layer of photo imageable ink is patterned to expose deposition sites on the traces, within which are formed electrically conductive fingers.

Abstract: The invention intends to provide a TFT having a gate insulating film which has a high dielectric withstand voltage and can ensure a desired carrier mobility in an adjacent semiconductor active film. A gate electrode and a semiconductor active film are formed on a transparent substrate with a gate insulating film, which is formed of two layered insulating films, held between them. The gate insulating film is made up of a first gate insulating film which improves a withstand voltage between the gate electrode and the semiconductor active film, and a second gate insulating film which improves an interface characteristic between the gate insulating film and the semiconductor active film. The first and second gate insulating films are each formed of a SiNx film. The optical band gap of the first gate insulating film has a value in the range of 3.0 to 4.5 eV, and the optical band gap of the second gate insulating film has a value in the range of 5.0 to 5.3 eV.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip and a laminated structure, wherein the chip includes a conductive pad, the laminated structure includes a conductive trace, an insulative base and a metal base, the conductive trace includes a routing line and a bumped terminal, the metal base and the routing line are disposed on opposite sides of the insulative base, and the bumped terminal includes a cavity that extends through the insulative base and into the metal base, removing a portion of the metal base that contacts the bumped terminal, and forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: The present invention relates to a method of forming a diode (2) for integration with a semiconductor device comprising the steps of providing a layer (4) of semiconductor material, forming a dielectric layer (6) over the layer of semiconductor material, introducing a first conductivity type dopant into the dielectric layer (6), forming a semi-conductive layer (8) over the dielectric layer (6), introducing a second conductivity type dopant into a first region (12) of the semi-conductive layer and re-distributing the first conductivity type dopant from the dielectric layer (6) into the semi-conductive layer (8) so as to form a second region (18) of the first conductivity type dopant in the semi-conductive layer (8), the second region (18) being adjacent the first region (12) so as to provide a P/N junction of the diode (2).

Abstract: A method of making a permeable base transistor (PBT) is disclosed. According to the method, a semiconductor substrate is provided, a base layer is provided on the substrate, and a semiconductor layer is grown over the base layer. The base layer includes metallic nanotubes, which may be grown or deposited on the semiconductor substrate. The nanotube base layer separates emitter and collector layers of semiconductor material.

Abstract: There is provided a film formation apparatus which is capable of forming an EL layer using an EL material with high purity. The EL material is purified by sublimation immediately before film formation in the film formation apparatus, to thereby remove oxygen, water, and another impurity, which are included in the EL material. Also, when film formation is performed using the EL material (high purity EL material) obtained by purifying with sublimation as an evaporation source, a high purity EL layer can be formed.

Abstract: A method for achieving a uniform planar surface by a chemical mechanical polish includes surrounding an active area or array to be polished with a border of the active material such that the border is wider than a single active area within the array and is preferably spaced from the outermost active area by the same distance as the distance between active areas within the array.

Abstract: A semiconductor device 100 includes a low-k dielectric insulator 104. In the preferred embodiment, a low-k dielectric material 104 is deposited. This material 104 is then cured using a plasma cure step. The cure process causes the density of the top portion 106 of layer 104 to be increased. The higher density portion 106, however, also has a higher dielectric constant. As a result, the dielectric constant of the layer 104 can be reduced by removing this higher density portion 106. This leads to a lower dielectric constant (e.g., less than about 3) of the bulk film.

Abstract: The present invention provides a method for depositing a metal film capable of suppressing oxygen from remaining within the metal film and preventing clustering of the metal film due to a low temperature deposition by employing a chemical vapor deposition process and a method for depositing a Ru film using the CVD process. The present invention provides a method for depositing a metal film by using a chemical vapor deposition process, including the steps of: loading a substrate to a reactor where a metal film will be deposited; heating the substrate to densify the metal film as simultaneous to a deposition of the metal film; and depositing the metal film on the substrate by adding a precursor of the metal film and a reaction gas having a reducing ability to the heated substrate.

Abstract: A polishing pad conditioner cleaning method and an apparatus for effectively removing particles from a polishing pad conditioner. The polishing pad conditioner is immersed into a cleaning liquid contained in a cleaning bath. The cleaning liquid is continuously supplied into the cleaning bath. An inert gas is injected into the cleaning liquid from a bottom of the cleaning bath. The injected inert gas bubbles the cleaning liquid, so that the particles sticking to the polishing pad conditioner are removed and overflow from the cleaning bath. The polishing pad conditioner is effectively cleaned, so that formation of particles and scratches on a wafer are reduced when a polishing process is subsequently carried out using the cleaned polishing pad conditioner.

Abstract: In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.