Abstract: A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself.

Abstract: A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be "disabled" by an inactive enable signal so they output a constant "0" level for the differential output clock. This disabling feature of the differential clock receiver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.

Abstract: A semiconductor integrated circuit is constructed with composite pass-transistor logic circuits serving as elementary circuit units each including a plurality of pass-transistor logic trees and a multiple-input logic gate. A wide variety of logical operations, even complex opearations, can be efficiently expressed using the composite pass-transistor logic circuit, and the resultant logic circuit can operate at a high speed. Thus, the semiconductor integrated circuit of the present invention can realize various logic functions required for various users in an efficient fashion. The present invention is particularly useful when applied to a field-programmable gate array integrated circuit, since complex logical operations can be expressed in a simple and efficient fashion by the composite pass-transistor logic circuits. The gate array integrated circuit obtained in accordance with the present invention can operate at a high speed with low power consumption.

Abstract: A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.

Abstract: Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance. Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance of an interface circuit output buffer comprises: digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance, and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.

Abstract: A receiver device includes two input circuits, connected in parallel, for receiving digital information in the form of electrical differential binary signals within a broad range of common-mode voltages. The input circuits in turn include transistors in differential input arrangements for receiving the signals. The transistors of input circuits are of one and the same type, so that the receiver device is capable of handling higher speeds. Controlled activation and deactivation of a first one of the input circuits further enhances the speed capabilities of the receiver device.

Abstract: An input circuit (20) and a method for protecting the input circuit (20) from positive and negative overvoltages. The input circuit (20) includes an N-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (12), a P-channel MOSFET (13), a Zener diode (21), and a diode-connected transistor (22). The P-channel MOSFET (13) protects the N-channel MOSFET (12) from negative overvoltages. The Zener diode (21) and the diode-connected transistor (22) protect the N-channel MOSFET (12) from positive overvoltages. In addition, the Zener diode (21) protects the P-channel MOSFET (13) from positive overvoltages.

Abstract: An electronic apparatus is disclosed having: a plurality of electronic devices with the same or different internal voltages; an interconnection between two or more of the plurality of electronic devices; each of said two or more electronic devices has an internal voltage; driver and receiver circuits which send and receive signals at a selectable communication voltage levels for interfacing between said two or more electronic devices, at a common communication voltage which is less than the highest value of said internal voltages of said two or more electronic devices; a circuit for configuring the driver and receiver circuits; and the driver circuit are configured to have a substantially constant output impedance independent of their output voltage.

Abstract: A level shift circuit which drops the output voltage of a prior stage circuit to an input voltage level required at a next stage circuit includes a source follower enhancement-type FET, a gate of which is connected as an input terminal, a drain of which is connected to a positive power supply, and a source of which is connected to an anode of a level shift diode; a current adjusting enhancement-type FET, a drain of which is connected to a cathode of the level shift diode, a drain and a gate of which are connected to each other through a constant current source, and a source of which is connected to a negative power supply, an out-put terminal being taken from the connection node of the level shift diode and the constant current source; and a resistor connected between the constant current source and the negative power supply, the current adjusting enhancement-type FET having its gate-to-source voltage controlled by the current flowing through the resistor, thereby adjusting the current flowing through the sou

Abstract: The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

Abstract: A semiconductor integrated circuit has an integrally formed logic circuit that is controlled by clock signals. The semiconductor integrated circuit includes a clock signal delay device that generates a plurality of clock signals having phases that are shifted from each other by a small amount with respect to a reference clock signal. The logic circuit is divided into a plurality (N number) of circuit blocks so that each of the circuit blocks is controlled by each of the associated plurality of clock signals to reduce noises. Noises in a CMOS integrated circuit are also reduced by controlled reference clock signals. A CMOS integrated circuit includes at least one CMOS gate with an input terminal being commonly connected to gates of a PMOS transistor and an NMOS transistor, and a latch circuit for transmitting data to the input terminal of the CMOS gate by clock signal control.

Abstract: The present invention provides a method of providing two different modes of operation for an output driver on an integrated circuit. A first mode provides an open drain driver, such as an enhanced GTL+ driver, for high-speed data transmission. A second mode provides a totem pole output driver, such as a TTL or a LVTLL driver, which does not require additional circuitry for external terminations, as is required for open drain drivers. Thus, one embodiment of the present invention can be characterized as a method of providing a dual mode output from an integrated circuit. This method includes receiving an output mode signal indicating an enhanced GTL+ output mode or a totem pole output mode. This method also includes providing an enhanced GTL+ output signal if the mode signal indicates the enhanced GTL+ output mode, and providing a totem pole output signal if the mode signal indicates the totem pole output mode.

Abstract: The present invention provides an apparatus for providing two different modes of operation for an output driver on an integrated circuit. A first mode provides an open drain driver, such as an enhanced GTL+ driver, for high-speed data transmission. A second mode provides a totem pole output driver, such as a TTL or a LVTLL driver, which does not require additional circuitry for external terminations, as is required for open drain drivers. Thus, one embodiment of the present invention can be characterized as an integrated circuit with an output buffer having a first mode that provides a driver for an open drain bus, and a second mode that provides a totem pole output. This output buffer receives a signal to be outputted from the integrated circuit and a mode select signal that selects between the first mode and the second mode.

Abstract: An asynchronous register with embedded acknowledge collection is disclosed. The asynchronous register includes a data threshold circuit for generating data or NULL values at an output signal line based upon an evaluation of at least one data input value and an acknowledgment collection circuit, embedded in the data threshold circuit, for collecting a plurality of acknowledge signals and resolving the acknowledge signals for controlling, in combination with the at least one data input value, the passing of the data or NULL values to the output signal line. The acknowledgment collection circuit includes an M of N acknowledge collection circuit, wherein N is an integer representing the number of acknowledge signals being resolved and M representing a threshold, wherein M.ltoreq.N.

Abstract: An integrated circuit having a DC current test function operates at a core supply voltage and interfaces at an input-output (I/O) supply voltage. The I/O supply voltage is greater than the core supply voltage. The integrated circuit includes a buffer, a voltage level shifting circuit and a pull-up circuit. The buffer is coupled between a core terminal and a pad terminal. The pad terminal has a voltage swing which is substantially equal to the I/O supply voltage. The voltage level shifting circuit has a test signal input with a voltage swing substantially equal to the core supply voltage and a test signal output with a voltage swing from the I/O supply voltage to a selected bias voltage. The pull-up circuit is coupled to the pad terminal and has a control terminal coupled to the test signal output.

Abstract: A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations.

Abstract: Various embodiments of a programmable logic device (PLD) capable of being dynamically partially reconfigured are disclosed. The PLD provides circuitry for changing its configuration data in whole or in part without halting the operation nor losing any of the logic state of the PLD. In one embodiment, data injection circuitry are added to a FIFO architecture to allow the user to inject data at random locations without disturbing the functionality of the PLD. In another embodiment, the PLD architecture is designed to provide for address wide or frame wide accessing of configuration bits. This allows for address wide configuration and reconfiguration.

Abstract: A programming method of a programmable logic device (PLD) to enable system recovery after power failure is provided. Key configuration bits controlling output enable signals of the PLD are programmed at a different time than all other configuration bits in the PLD. If those key bits are unprogrammed, the PLD behaves identically to a fully erased device. Thus, by programming the key configuration bits after all other bits are successfully programmed, any potential damage to the system is virtually eliminated. In this manner, if the main programming sequence is interrupted, the PLD will power up with partial internal activity, but no active output signals. Moreover, even if the interruption occurs during the programming of these few bits, the result is only a partial activation of output signals which is significantly better than the activation of output signals with incorrect functions.

Abstract: An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein the input circuit comprises a plurality of FETs connected between a first voltage node and a dynamic node of a logic circuit. The gate electrode of each input circuit FET is connected to one of the input nodes. Precharged FET is connected between the dynamic node and a second voltage node. The precharge FET is configured to conduct a current for precharging the dynamic node to a predetermined voltage. An inverter is coupled between the dynamic node and an output node. A precharge control circuit is connected in a feedback path between the output node and the precharge FET. The precharge control signal activates the precharge control FET in response to a RESET pulse width and deactivates the precharge FET in response to the voltage on the dynamic node.

Abstract: A switchable active termination device internally mounted within a peripheral device and electrically connected to the end of a Small Computer Systems Interface (SCSI) bus cable. Through use of a pair of SCSI active terminator circuit chips, the termination device actively terminates the data lines of the bus cable in a first operating mode in response to a first digital command by providing precise resistive pull-up to a predetermined value on each data line. In a second mode of operation responsive to a second digital command, the termination device disconnects all terminating resistors. Activation of the termination modes is logically driven from an included switch, with visual indication of the presence of an active termination state provided by a light emitting diode.