Patents Examined by Rita Ann Ziemer
  • Patent number: 6314531
    Abstract: A method and system for emulating network latency, packet corruption, packet shuffling, packet loss and network congestion is introduced so that network connected multi-computer software systems can be tested and debugged in a cost effective and efficient manner. This network emulator requires no changes to the software being tested and requires only modifications to the MAC to IP mapping tables of the computers running the software to be tested. IT requires no modification to the communication stacks of the computers involved. The changes to these tables cause packets to be redirected to an emulator host computer where they can be delayed, deleted, corrupted or shuffled prior to delivery to their final destination.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: November 6, 2001
    Assignee: International Business Machines Corporation
    Inventor: Paul Regis Kram
  • Patent number: 6049887
    Abstract: A method of transmitting a signal from a first clock domain to a second clock domain commences with the generation of first and second clock signals. The first and second clock signals are substantially synchronous and have respective frequencies that are non-integer multiples. A first signal, which is generated in the first clock domain responsive to a transition of the first clock signal that is substantially coincident with a transition of the second clock signal, is prevented from being latched in the second clock domain responsive to the transition of the second clock signal. The first clock signal is prevented from being latched for a time period which is greater than a maximum clock skew which may exist between the first and second clock signals.
    Type: Grant
    Filed: December 4, 1997
    Date of Patent: April 11, 2000
    Assignee: Intel Corporation
    Inventors: Narendra Khandekar, Ashish S. Gadagkar, Robert F. Kubick, Vincent E. VonBokern, Manish Muthal