Patents Examined by Rita Ziemes
  • Patent number: 6321343
    Abstract: A maximum flight time measuring circuit constituted by a first delay circuit for delaying a system clock and controlling its delay time in accordance with a strobe clock from DIMMs and a delayline register circuit for storing a delayed state in the delay circuit, and a second delay circuit are provided. Contents of the delayline register circuit are input to the second delay circuit, which is controlled to generate the same delay as that of the first delay circuit. The output of the second delay circuit is supplied as a data fetch signal to a control buffer for receiving read data DQ from the DIMMs.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: November 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda