Abstract: A method for manufacturing a solar cell includes forming a conductive type region on one surface of a semiconductor substrate, and forming an electrode on the conductive type region, wherein the forming of the electrode includes forming a metal layer on an entire area of the conductive type region, forming a printed electrode layer having a pattern on the electrode layer, and forming an electrode layer between the conductive type region and the printed electrode layer, wherein the forming of the electrode layer includes patterning the metal layer by using the printed electrode layer as a mask.

Abstract: A semiconductor structure is provided that can be used for DNA sequencing detection. The semiconductor structure includes a doped epitaxial source semiconductor material structure located on a first portion of a semiconductor substrate and a doped epitaxial drain semiconductor material structure located on a second portion of the semiconductor substrate. A gate dielectric portion is located on a third portion of the semiconductor substrate and positioned between the doped epitaxial source semiconductor material structure and the doped epitaxial drain semiconductor material structure. A non-stick nucleotide, DNA and DNA polymerase material structure is located atop the doped epitaxial source semiconductor material structure and atop the doped epitaxial drain semiconductor material structure, wherein a cavity is present in the non-stick nucleotide, DNA and DNA polymerase material structure that exposes a topmost surface of the gate dielectric portion.

Abstract: An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.

Abstract: Computational methods and systems for generating virtual smart-meter data from operational data collected by intelligent controllers in buildings that do not have smart meters are disclosed. Methods and systems include collecting operational data from a number of intelligent controllers and collecting smart-meter data from a number of smart meters associated with the intelligent controllers. The collected operational data and associated smart-meter data are used to generate a mathematical model relating operational data to smart-meter data. The mathematical model can be used to calculate virtual smart-meter data from operational data collected by an intelligent controller located in a building that does not have a smart meter.

Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

Abstract: An information handling system includes an electrical connector to mate with terminals of a data storage device. The system further includes a temperature sensor integrated at the electrical connector. The temperature sensor is arranged to thermally couple to an exterior surface of the data storage device when the data storage device is fully inserted into the electrical connector.

Abstract: A luminescent material mixture has a first luminescent material and a second luminescent material, wherein, under excitation with blue light, an emission spectrum of the first luminescent material has a relative intensity maximum in a yellowish-green region of the spectrum at a wavelength of greater than or equal to 540 nm and less than or equal to 560 nm and an emission spectrum of the second luminescent material has a relative intensity maximum in an orange-red region of the spectrum at a wavelength of greater than or equal to 600 nm and less than or equal to 620 nm.

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a substrate having a solder mask. A plurality of pillar bases are formed on the solder mask, and a plurality of solder pillars are applied to the pillar bases. The plurality of solder pillars support one or more semiconductor die above the substrate and the number of solder pillars prevent stresses in the one or more semiconductor die which could otherwise damage the semiconductor die.

Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

Abstract: A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth.

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.

Abstract: Embodiments of sensing devices include one or more integrated circuit (IC) die, a housing, and a fluid barrier material. Each IC die includes an electrode-bearing surface and a contact surface. One of the die includes an SFET with a sensing electrode proximate to the electrode-bearing surface. The same or a different die includes a reference electrode proximate to the electrode-bearing surface. The die(s) also include IC contacts at the contact surface(s), and conductive structures coupled between the SFET, the reference electrode, and the IC contacts. The housing includes a mounting surface, and housing contacts formed at the mounting surface. The IC contacts are coupled to the housing contacts. The fluid barrier material is positioned between the mounting surface and the IC die. The fluid barrier material provides a fluid barrier between the IC and housing contacts and a space that encompasses the sensing electrode and the reference electrode.

Abstract: A memory device includes a plurality of bit lines, including first and second bit lines, extending in a first direction away from a substrate, a plurality of word lines, including first and second word lines, extending in a second direction crossing the first direction and substantially parallel to a surface of the substrate, a first variable resistance film between the first word line and the first bit line and a second variable resistance film between the second word line and the second bit line, an insulating material electrically isolating the first and second word lines and the first and second bit lines, and a plurality of air gaps between the first and second bit lines.

Abstract: A semiconductor structure for use in single molecule real time DNA sequencing technology is provided. The structure includes a semiconductor substrate including a first region and an adjoining second region. A photodetector is present in the first region and a plurality of semiconductor devices is present in the second region. A contact wire is located on a surface of a dielectric material that surrounds the photodetector and contacts a topmost surface of the photodetector and a portion of one of the semiconductor devices. An interconnect structure is located above the first region and the second region, and a metal layer is located atop the interconnect structure. The metal layer has a zero waveguide module located above the first region of the semiconductor substrate. A DNA polymerase can be present at the bottom of the zero waveguide module.

Abstract: Disclosed herein are a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes: a substrate, a light-emitting layer disposed on a surface of the substrate and including a first type semiconductor layer, an active layer, and a second type semiconductor layer, a first bump disposed on the first type semiconductor layer and a second bump disposed the second type semiconductor layer, a protective layer covering at least the light-emitting layer, and a first bump pad and a second bump pad disposed on the protective layer and connected to the first bump and the second bump, respectively.

Abstract: A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.

Abstract: Semiconductor devices and methods of making the same include forming a gate structure on a thin semiconductor layer. Additional semiconductor material is formed on the thin semiconductor layer. The thin semiconductor layer is etched back and the additional semiconductor material to form source and drain regions and a channel region, with notches separating the source and drain region from the channel region.

Abstract: Package structures and methods of forming package structures are described. A method includes depositing and patterning a first dielectric material. The first dielectric material is deposited in first and second package component regions and in a scribe line region. The scribe line region is disposed between the first and second package component regions. The patterning the first dielectric material forms a first dielectric layer in each of the first and second package component regions and a dummy block in the scribe line region. The dummy block is separated from the first dielectric layer in each of the first and second package component regions. The method further includes forming a metallization pattern on the first dielectric layer; depositing a second dielectric material on the first dielectric layer and the metallization pattern; and patterning the second dielectric material to form a second dielectric layer.

Abstract: A lighting device includes a base, at least one light emitting chip, at least one optical member covering the light emitting chip, and a thermally conductive adhesive layer. The thermally conductive adhesive layer has opposite sides directly contacting the light emitting chip and the base, respectively.