Abstract: An optoelectronic device manufacturing method including the steps of: a) forming an active diode stack including first and second of opposite conductivity types; b) forming an integrated control circuit including a plurality of elementary control cells each including at least one MOS transistor; c) after steps a) and b), transferring the integrated control circuit onto the upper surface of the active diode stack; and d) after step c), forming trenches extending vertically through the integrated control circuit and emerging into or onto the first layer and delimiting a plurality of pixels each including a diode and an elementary control cell.

Abstract: An illumination apparatus is manufactured by selectively removing passive optical nanostructures from a monolithic array of light-emitting elements while preserving their relative spatial position. The nanostructures are selected such that, in at least one direction, for at least one pair of the selectively removed passive optical nanostructures, for each respective pair there is at least one nanostructure that is not selected that was positioned in the monolithic array between the pair of selectively removed passive optical nanostructures in the at least one direction, forming a non-monolithic array of passive optical nanostructures with the selectively removed passive optical nanostructures while preserving their relative spatial position, and aligning each of the passive optical nanostructures of the non-monolithic array with a respective light-emitting element of the non-monolithic array of light-emitting elements.

Abstract: A display device includes a substrate, a plurality of pixels provided to the substrate, a plurality of light emitting elements provided to each of the pixels, and a cathode electrode covering the light emitting elements. The light emitting elements each include a p-type cladding layer, an active layer, an n-type cladding layer, and a high-resistance layer stacked in order on the substrate, sheet resistance of the high-resistance layer is higher than sheet resistance of the n-type cladding layer, an upper surface of the n-type cladding layer has a plurality of recesses, and the cathode electrode covers the high-resistance layer and is directly coupled to the recesses and a peripheral part of the n-type cladding layer.

Abstract: A micro light-emitting device display apparatus includes a driving substrate and a plurality of micro light-emitting devices. The micro light-emitting devices are disposed on the driving substrate. The micro light-emitting devices include a plurality of first, second and third micro light-emitting devices. Each of the first, the second and the third micro light-emitting devices respectively has a plurality of first, second, and third light-emitting regions independently controlled. A first light-emitting region of a first micro light-emitting device, a second light-emitting region of a second micro light-emitting device, and a third light-emitting region of a third micro light-emitting device are located in a first pixel region. A first light-emitting region of another first micro light-emitting device, a second light-emitting region of another second micro light-emitting device, and another third light-emitting region of the third micro light-emitting device are located in a second pixel region.

Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

Abstract: Methods of forming a semiconductor device comprising a lead-frame having a die pad having at least one electrically conductive die pad area and an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

Abstract: A display device having high light-extraction efficiency is provided. A low-power display device is provided. In a red or green pixel included in the display device, a light-emitting element, an optically functional layer, and a wavelength-conversion layer are stacked in this order. The light-emitting element emits blue light, the optically functional layer transmits the blue light and reflects red and green light, and the wavelength-conversion layer converts the blue light into red or green light. The blue light emitted by the light-emitting element passes through the optically functional layer and enters the wavelength-conversion layer, and red or green light is emitted to the outside. The red or green light emitted from the wavelength-conversion layer to the optically functional layer side is reflected by the optically functional layer and emitted to the outside, which improves light-extraction efficiency.

Abstract: Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n+-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.

Abstract: A method of manufacturing an electronic device includes the steps of providing a conductive carrier with at least one electronic element disposed thereon, picking up the at least one electronic element, setting the conductive carrier to have a ground voltage at least in the step of picking up the at least one electronic element, and transferring the at least one electronic element to a target substrate.

Abstract: Disclosed is a micro light-emitting component, a micro light-emitting diode, and a transfer layer. The transfer layer has a recess for receiving the micro light-emitting diode to permit the micro light-emitting diode to be retained by the transfer layer, and is transformable from a first state, in which the transfer layer is deformed by the micro light-emitting diode to form the recess, to a second state, in which the micro light-emitting diode received in the recess is retained by the transfer layer. Also disclosed are micro light-emitting component matrix and a method for manufacturing the micro light-emitting component matrix.

Abstract: A micro light-emitting diode display includes a first-type semiconductor base layer, a plurality of semiconductor light-emitting mesas dispersedly disposed on the first-type semiconductor base layer, a semiconductor heightening portion disposed on the first-type semiconductor base layer, a first bonding metal layer disposed on the semiconductor heightening portion, and a plurality of second bonding metal layers respectively disposed on the semiconductor light-emitting mesas. A top surface of the semiconductor heightening portion and a plurality of top surfaces of the semiconductor light-emitting mesas facing away from the first-type semiconductor base layer are coplanar. The top surface of the semiconductor heightening portion forms a first bonding surface adjacent to the first bonding metal layer.

Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

Abstract: A semiconductor module, including a ceramic board, a circuit pattern metal plate formed on a principal surface of the ceramic board, an external connection terminal bonded, via a solder, to the circuit pattern metal plate, and a low linear expansion coefficient metal plate located between the circuit pattern metal plate and the external connection terminal. The circuit pattern metal plate has a first edge portion and a second edge portion, which are opposite to each other and are respectively at a first side and a second side of the circuit pattern metal plate. The low linear expansion coefficient metal plate has a linear expansion coefficient lower than a linear expansion coefficient of the circuit pattern metal plate.

Abstract: Described are light emitting diode (LED) devices including a combination of electroluminescent and photo-luminescent active regions in the same wafer to provide LEDs with emission spectra that are adjustable after epitaxial growth. The LED device includes a multilayer anode contact comprising a reflecting metal and at least one transparent conducting oxide layer in between the metal and the p-type layer surface. The thickness of the transparent conducting oxide layer may vary for LEDs fabricated with different emission spectra.

Abstract: A light emitting device includes a backplane, light emitting diodes (LEDs) attached to a front side of the backplane, and a micro lens array (MLA) located over the LEDs, the MLA containing unit lenses that have a smaller maximum diameter than a maximum lateral widths of the respective LEDs.

Abstract: A light emitting device includes an LED die and a wavelength conversion layer. The LED die has a light emitting top surface and light emitting side surfaces. The wavelength conversion layer contains quantum dots and a photosensitive material, and is located on the light emitting top surface. A light emitting module including multiple light emitting devices is also disclosed.

Abstract: Photo-emitting and/or photo-receiving diode array device, comprising: a stack of first and second semiconductor layers doped according to different types; first trenches passing through the stack and surrounding a region of the stack wherein several diodes are formed; dielectric portions arranged in the first trenches and covering lateral flanks of said region over the entire thickness of the second layer and a first part of the thickness of the first layer; first electrically conductive portions arranged in the first trenches and covering the lateral flanks of said region over a second part of the thickness of the first layer, and forming first electrodes of the diodes of said region; at least one second trench partially passing through the first layer and separating the portions of the first layer from the diodes of said region.

Abstract: With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. Due to the increase in the numbers of gate lines and signal lines, it is difficult to mount an IC chip having a driver circuit for driving the gate and signal lines by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit for driving the pixel portion are formed over one substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor is used. The driver circuit as well as the pixel portion is provided over the same substrate, whereby manufacturing costs are reduced.

Abstract: A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.

Abstract: A display device includes a pixel array, at least one flexible substrate, and at least one optical blocking layer. The flexible substrate is located below the pixel array. The optical blocking layer is located between the flexible substrate and the pixel array. The optical blocking layer includes a first sub-layer and a second sub-layer. The first sub-layer is located between the second sub-layer and the flexible substrate, and a refractive index of the first sub-layer is different from a refractive index of the second sub-layer.