Abstract: A method includes selecting a particular ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B # pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. Each computing device is operable to access one or more memory blocks within the storage devices and maintain a registry over the same one or more memory blocks. The registry may be adaptively resized according to the access of the one or more memory blocks.

Abstract: Provided are a computer program product, system, and method for determining tracks to prestage into cache from a storage. Information is provided related to determining tracks to prestage from the storage to the cache in a stage group of sequential tracks including a trigger track comprising a track number in the stage group at which to start prestaging tracks and Input/Output (I/O) activity information to a machine learning module. A new trigger track in the stage group at which to start prestaging tracks is received from the machine learning module having processed the provided information. The trigger track is set to the new trigger track. Tracks are prestaged in response to processing an access request to the trigger track in the stage group.

Abstract: A controller optimizes read threshold values for a memory device using domain transformation. The controller determines, for decoded data of each read operation, an asymmetric ratio (AR) and a number of unsatisfied checks (USCs), the AR indicating a ratio of a number of a first binary value to a number of a second binary value in the decoded data. The controller determines a Z-axis such that AR values of threshold sets are arranged in a set order along the Z-axis. The controller determines an optimum read threshold set using coordinate values on the Z-axis, which correspond to a set AR value and a set USC value.

Abstract: Trace recording based on data influxes to an outer-level cache and cache coherence protocol (CCP) transitions between inner caches. Example computing device(s) include a plurality of processing units, a plurality of (N-1)-level caches, and an N-level cache that is associated with two or more of the (N-1)-level caches and that is a backing store for the two or more (N-1)-level caches. Based at least on detecting influx(es) of data to a location in the N-level cache during execution across the processing units, the computing device(s) causes the influx(es) of data to be logged. The computing device(s) also causes one or more (N-1)-level CCP transitions between the two or more (N-1)-level caches to be logged. The (N-1)-level CCP transitions result from the location being accessed by two or more of the processing units.

Abstract: A partition command from one of a plurality of write partition command queues or a plurality of read partition command queues is received. The received partition command is issued to a command processor of the sequencer component to be applied to one of the one or more memory devices. Responsive to receiving the partition command of the plurality of write partition command queues, whether a timeout threshold criterion pertaining to the plurality of read partition command queues is satisfied is determined. Responsive to determining that the timeout threshold criterion pertaining to the plurality of read partition command queues is not satisfied, whether a write threshold criterion pertaining to the plurality of write partition command queues is satisfied is determined.

Abstract: Disclosed are systems and methods for providing read-modify-writes during relocation of overlapping of logical blocks. A method includes receiving a host write command from a host interface. The method also includes translating a logical block address for the host write command to a physical address on a device memory. The physical address corresponds to a plurality of indirection units. The method also includes, in accordance with a determination that the physical address does not correspond to an aligned address, processing a read-modify-write operation for one or more indirection units of the plurality of indirection units during a relocation, in accordance with a determination that a relocation block has an overlapping indirection unit with the one or more indirection units.

Abstract: A system can include a memory device and a processing device coupled with the memory device. The processing device can receive a command of a first type from a host system. The processing device can select a threshold criterion for the command of the first type based on a count of commands of a second type. The processing device can determine whether a second count of commands of the first type satisfies the threshold criterion and in response to the second count satisfying the threshold criterion, the processing logic can transmit a notification to the host system to refrain from transmitting the commands of the first type.

Abstract: Apparatuses and methods can be related to generating an asynchronous process topology in a memory device. The topology can be generated based on the results of a number of processes. The processes can be asynchronous given that the processing resources that implement the processes do not use a clock signal to generate the topology.

Abstract: Provided is a storage system including a plurality of controllers. The storage system adopts a write-once data storage system and can implement high Input/Output (I/O) processing performance while ensuring data consistency when a failure occurs. Before metadata duplication, recovery data including information necessary for performing roll forward or roll back is stored in each controller, and then the metadata duplication is performed. A recovery data storage processing and the metadata duplication are offloaded to a hardware accelerator.

Abstract: Techniques are disclosed relating to multi-activation techniques for wire operations with multiple partial writes. In some embodiments, a memory controller is configured to access data in a memory device that supports partial writes having a first size using read-modify-write operations and non-partial writes having a second size that is greater than the first size. In some embodiments, the memory controller is configured to queue a first write operation having the second size, where the first write operation includes multiple partial writes. In some embodiments, the memory controller is configured to send separate activate signals to the memory device to activate a bank of the memory device to perform different proper subsets of the multiple partial writes. This may allow interleaving of other accesses to a memory bank and merging of writes while waiting for a current activation, in some embodiments.

Abstract: A circuit for transmitting data includes a mode register data processing module, an external data transmission module, and an internal data transmission module provided in a memory array; the mode register data processing module is configured to write initial data into a reserved mode register in a mode register in response to a write enable command; and the external data transmission module is electrically connected to both the reserved mode register and the internal data transmission module, and is configured to write, in response to an enable signal, target data into the memory array via the internal data transmission module according to the initial data and a preset encoding rule, wherein a number of bytes of the target data is greater than a number of bytes of the initial data.

Abstract: Worker threads allocate at least some recycled cache slots of a local portion of a shared memory to the compute node to which the memory portion is local. More specifically, the recycled cache slots are allocated prior to receipt of the IO that the recycled cache slot will be used to service. The allocated recycled cache slots are added to primary queues of each compute node. If a primary queue is full then the worker thread adds the recycled cache slot, unallocated, to a secondary queue. Cache slots in the secondary queue can be claimed by any compute node associated with the shared memory. Cache slots in the primary queue can be used by the local compute node without sending test and set messages via the fabric that interconnects the compute nodes, thereby improving IO latency.

Abstract: A storage system and an operating method thereof are disclosed. The storage system includes a nonvolatile memory that stores data; a computing device to perform data processing on input data provided from the nonvolatile memory or a host outside the storage system; and a controller to control a writing operation and a reading operation of the nonvolatile memory, monitor an operating state of the computing device while the computing device is performing the data processing, and dynamically manage power of the computing device according to a monitoring result.

Abstract: Example implementations described herein are directed to a method and a system for storage allocation from a storage pool, the method involving, for receipt of a request for storage through an orchestrator communicatively coupled to a management system managing the storage pool, the request comprising user information and request characteristics information, the request characteristics information indicative of a use type for the request, determining a storage tier from the storage pool for the request based on the user information and the request characteristics information; and allocating a pool name and the storage tier in response to the request.

Abstract: A storage device includes: a nonvolatile memory configured to store map data; and a controller configured to divide map data to be uploaded among the map data into a plurality of map units and to process a normal read command queued in a command queue, after encoding a first map unit of the plurality of map units and before encoding a next map unit, among the plurality of map units, to be encoded after encoding of the first map unit is completed.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may fetch a first command from the host into a command queue, suspend execution of the first command when receiving a lock request for the first command from the host, and resume the execution of the first command when receiving an unlock request for the first command or after the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request.

Abstract: A data processor includes a staging buffer, a command queue, a picker, and an arbiter. The staging buffer receives and stores first memory access requests. The command queue stores second memory access requests, each indicating one of a plurality of ranks of a memory system. The picker picks among the first memory access requests in the staging buffer and provides selected ones of the first memory access requests to the command queue. The arbiter selects among the second memory access requests from the command queue based on at least a preference for accesses to a current rank of the memory system. The picker picks accesses to the current rank among the first memory access requests of the staging buffer and provides the selected ones of the first memory access requests to the command queue.

Abstract: Methods and systems for storing a set of two or more variable length data blocks in a memory. Each variable length data block having a maximum size of N*B, wherein N is an integer greater than or equal to two, and B is a maximum data size that can be written to the memory using a single memory access request. The methods include: storing, for each variable length data block of the set, the first P non-overlapping portions of size B of the variable length data block in a chunk of the memory allocated to that the variable length data block, wherein P is a minimum of (i) a number of non-overlapping portions of size B of the variable length data block and (ii) X which is an integer less than N; storing any remaining portions of the variable length data blocks in a remainder section of the memory that is shared between the variable length data blocks of the set; and storing, in a header section of the memory, information indicating the size of each of the variable length data blocks in the set.

Abstract: A method of programming data to a storage device including a nonvolatile memory device includes receiving first to third barrier commands from a host, receiving first to third data corresponding to the first to third barrier commands from the host, merging the first and second barrier commands and programming the first and second data to the nonvolatile memory device sequentially based on an order of the first and second barrier commands, verifying program completion of both the first and second data, mapping in mapping information of the first and second data when the programming of the first and second data is completed, and mapping out the information of both the first and second data when the programming of at least one of the first and second data is not complete, and programming the third data to the nonvolatile memory device after the mapping in or the mapping out.