Abstract: A method for fabricating a semiconductor device includes providing a substrate including first landing plugs and second landing plugs that are arrayed on a first line, forming a capping layer over the substrate, forming hole-type first trenches that expose the second landing plugs by selectively etching the capping layer, forming an insulation layer over the substrate including the first trenches, forming line-type second trenches that are stretched on the first line while overlapping with the first trenches by selectively etching the insulation layer, and forming a first conductive layer inside the second trenches.

Abstract: The invention relates to a method for equipping a process chamber in an apparatus for depositing at least one layer on a substrate held by a susceptor in the process chamber, process gases being introduced into the process chamber through a gas inlet element, in particular by means of a carrier gas, the process gases decomposing into decomposition products in the chamber, in particular on hot surfaces, the decomposition products comprising the components that form the layer. In order to improve the apparatus so that thick multi-layer structures can be deposited reproducibly in process steps that follow one another directly, it is proposed that a material is selected for the surface facing the process chamber at least of the wall of the process chamber that is opposite the susceptor, the optical reflectivity, optical absorptivity and optical transmissivity of which respectively correspond to those of the layer to be deposited during the layer growth.

Abstract: Methods for depositing metal in high aspect ratio features formed on a substrate are provided herein. In some embodiments, a method includes applying first RF power at VHF frequency to target comprising metal disposed above substrate to form plasma, applying DC power to target to direct plasma towards target, sputtering metal atoms from target using plasma while maintaining pressure in PVD chamber sufficient to ionize predominant portion of metal atoms, depositing first plurality of metal atoms on bottom surface of opening and on first surface of substrate, applying second RF power to redistribute at least some of first plurality from bottom surface to lower portion of sidewalls of the opening, and depositing second plurality of metal atoms on upper portion of sidewalls by reducing amount of ionized metal atoms in PVD chamber, wherein first and second pluralities form a first layer deposited on substantially all surfaces of opening.

Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.

Abstract: A method of manufacturing a silicon carbide semiconductor device of an embodiment includes: implanting ions in a silicon carbide substrate; performing first heating processing of the silicon carbide substrate in which the ions are implanted; and performing second heating processing of the silicon carbide substrate for which the first heating processing is performed, at a temperature lower than the first heating processing.

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

Abstract: A substrate depositing system and a method of using a substrate depositing system. A substrate depositing system includes a load-lock chamber for loading and unloading a substrate, at least one transfer chamber connected to the load-lock chamber and including a substrate transfer device configured to vertically transfer the substrate, and a pair of depositing chambers connected to opposite sides of the at least one transfer chamber and including a depositing source and a pair of substrate fixing devices, the substrate transfer device including a pair of substrate installing members.

Abstract: Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).

Abstract: A thin-film transistor device manufacturing method forms a plurality of gate electrodes above a substrate. A silicon nitride layer is formed on the plurality of gate electrodes. A silicon oxide layer is formed on the silicon nitride layer. An amorphous silicon layer is formed on the silicon oxide layer. The amorphous silicon layer is crystallized using predetermined laser light to produce a crystalline silicon layer. A source electrode and a drain electrode are formed on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes. A film thickness of the silicon oxide layer, a film thickness of the silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy predetermined conditional expressions.

Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract: A substrate holder has two holder constituting bodies, each having a plurality of columns arranged on an imaginary circle, and substrate holding sections that hold circumferential portions of respective substrates. The holder constituting bodies hold the substrates so that either their front surfaces or their back surfaces face upward with a substrate having an upward facing front and a substrate having an upward facing rear being alternately arranged in a vertical direction. At least one of the holder constituting bodies moves in the vertical direction to change the positions of the holder constituting bodies relative to each other. A distance between a first pair of vertically adjacent substrates with their respective front surfaces facing each other is set to ensure treatment uniformity, and to be larger than a distance between a second pair of vertically adjacent substrates with their respective back surfaces facing each other.

Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

Abstract: A crystalline silicon thin film is formed by irradiating a silicon thin film with a laser beam. The laser beam is a continuous wave laser beam. An intensity distribution of the laser beam in a first region about a center of the intensity distribution is symmetric on an anterior side and a posterior side of the center. The intensity distribution in a second region about the center is asymmetric on the anterior side and the posterior side. The first region is from the maximum intensity of the laser beam at the center to an intensity half of the maximum intensity. The second region is at most equal to the half of the maximum intensity of the laser beam. In the second region, an integral intensity value on the posterior side is larger than on the anterior side.

Abstract: In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of sticky material. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.

Abstract: A composite article with at least one high integrity protective coating, the high integrity protective coating having at least one planarizing layer and at least one organic-inorganic composition barrier coating layer. A method for depositing a high integrity protective coating.

Abstract: A method for manufacturing a thin film photoelectric conversion module includes the steps of forming a plurality of photoelectric conversion elements connected in series on a substrate, and carrying out reverse bias processing simultaneously on a group of photoelectric conversion elements including a plurality of the photoelectric conversion elements positioned with one or a plurality of the photoelectric conversion elements interposed between each of them, by applying a plurality of voltages electrically isolated from one another to the group of photoelectric conversion elements.

Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.

Abstract: The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing sidewalls of the opening are lined with a second material, with monocrystalline material being exposed at a base of the second material-lined opening. A silicon-comprising layer is epitaxially grown from the exposed monocrystalline material within the second material-lined opening. At least a portion of the second material lining is in situ removed. Other aspects and implementations are contemplated.

Abstract: A silicon wafer after being subjected to mirror polishing but before being subjected to form an epitaxial layer thereon is subjected to an ozone gas treatment that oxidizes a surface of the silicon wafer by use of ozone gas, a hydrofluoric acid gas treatment that dissolves and removes the oxidized surface of the silicon wafer by use of hydrofluoric acid gas, and a washing treatment that removes foreign substances remaining on the surface of the silicon wafer, whereby PIDs (Polishing Induced Defects) generated by the mirror polishing are forcedly oxidized, dissolved and removed. By performing epitaxial treatment thereafter, PID-induced convex defects can be prevented from generating on the surface of the epitaxial wafer.