Abstract: A large array probe/contact having spring characteristics for relieving stress in the contact caused, for example, by temperature change is fabricated using a unique combination of semiconductor fabrication operations. The contacts in the array have a “U” shaped resilient portion, are fixed at one end to a substrate and have an accessible low electrical noise contact tip. The contacts are encapsulated on the substrate in an elastomer to provide additional stress relief resilience, support and protection from damage during handling.

Abstract: The invention is a test apparatus incorporating high current test pins, forced into contact with a circuit assembly under test by opposing compliant pressure pins. An advantageous test pin for low voltage, high current testing is a solid, one piece test pin. The solid test pin, when supplied with adequate contact force, provides both low resistance and low inductance. The required compliant force is applied to the test circuit, opposite and substantially in line with the solid test pin, by a compliant pressure pin. Since the test pin does not supply the compliant force, it can be designed primarily for the desired electrical parameters of the test contact. The only mechanical considerations for the conductive solid pin are the amount of desired surface contact area, the dominant mechanical parameter in setting the contact resistance, and the body dimensions, which determine the resistance and inductance of the pin itself.

Abstract: A semiconductor chip is provided with a phase comparison circuit (1), in addition to an integrated circuit implementing a normal operation. The phase comparison circuit (1) compares phases between an internal signal (A) of the integrated circuit and an external signal and outputs a monitor signal (MONSIG) expressing the result of this comparison outward from the semiconductor chip. Thus, the phase of the internal signal (A) of the integrated circuit can be directly detected.

Abstract: A device-under test (DUT) assembly includes a DUT board having a plurality of spine assemblies. Each spine assembly has a first outer face, a second outer face, and a first plurality of contacts on at least one of the first and second outer faces in electrical contact with a subset of the first signal lines. A connector assembly includes a plurality of clamping assemblies arranged to receive the plurality of spine assemblies. Each clamping assembly includes a first inner face, a second inner face, and a second plurality of contacts on at least one of the first and second inner faces in electrical contact with a subset of the second signal lines. Electrical connections between the first and second contacts are formed when the first and second inner faces of each clamping assembly are clamped to the first and second outer faces of the corresponding spine assembly.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conducive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: An electrical energy meter comprises an electrically insulating housing (10) for securing relative to least two mains cables (22,24) each having a conductive core surrounded by a sheath of insulating material. The housing includes respective electrical contacts for piercing the insulating sheath of each cable, a current probe for measuring current flowing in at least one of the cables, and circuit means for calculating and displaying electrical energy as a function of the voltage across the contacts and the output of the current probe. An improved current probe is employed comprising a series of Rogowski coils equally spaced around the circumference of a circle, with the gap between two adjacent coils permitting the current-carrying conductor to be introduced into the loop. An alternative current probe employs two such concentric loops of coils, enabling compensation for the effects of external current source pickup.

Abstract: A comparator circuit includes at least one transconductance stage that receives two test voltages and two reference voltages. The transconductance stage produces two test currents that are proportional to the test voltages and two reference currents. A switching circuit is coupled to the transconductance stage. The switching circuit has two output terminals that are coupled to a conventional comparator stage. The switching circuit can combine the test currents with the reference currents to realize a differential swing comparison mode and a common-mode comparison mode as required for testing differential signals. Moreover, by disabling appropriate output signals from the at least one transconductance stage, a single-ended comparison mode is realized. By using two identical transconductance amplifiers, the non-linearity of the transconductance stage is advantageously canceled out.

Abstract: The temperature of multiple integrated circuit modules is regulated by a heat exchanger which is sequentially squeezed against, and separated from, a respective uneven contact surface on each of the modules. The heat exchanger has a face of a malleable metal that stays in a solid state and deforms while the squeezing occurs. The surface of the malleable metal has a coating of a release agent that prevents the malleable metal from sticking to the contact surface.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibrations method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: A semiconductor inspection device inspects a semiconductor device to determine whether the semiconductor device is good or bad. The semiconductor inspection device has a semiconductor inspection unit including first to M-th semiconductor inspection circuits (M: an integer not smaller than 2). The first to M-th semiconductor inspection circuits are configured to perform inspections on the semiconductor device for first to M-th inspection items, respectively. The first to M-th inspection items are different from each other. The semiconductor inspection device also includes a tester for receiving outputs from the first to M-th inspection circuits, respectively, to judge whether the semiconductor device passes or fails for each of the first to M-th inspection items. The tester further judges whether the semiconductor device is good or not based on the judgment results for the first to M-th inspection items.

Abstract: An electronic device tester channel transmits a single test signal to multiple terminals of electronic devices under test (DUTs) through a set of isolation resistors. The tester channel employs feedback to automatically adjust the test signal voltage to compensate for affects of faults at any of the DUT terminals to prevent the faults from substantially affecting the test signal voltage.

Abstract: An inspection terminal for accurately measuring a characteristic of an electronic chip component without causing an inner electrode layer constituting an external electrode of the electronic chip component to be exposed to the outside, an inspection method, and an inspection apparatus using the same, involves storing an electronic chip component in a storing portion of a turntable and sucking the electronic chip component by a sucking portion provided in a side guard. A linear edge portion of the inspection terminal is pressed from the bottom so as to abut against the external electrode of the electronic chip component. The linear edge portion is arranged to have an obtuse angle and is brought into contact with the external electrode such that the edge portion lies substantially parallel to the longitudinal direction of the external electrode.

Abstract: An integrated circuit chip can be thermally destroyed in a tester due to a defective pressed joint with a temperature regulating component. A method which prevents such destruction begins with the step of pressing the chip against the temperature regulating component within the tester. While the pressing step is occurring, thermal power is sent to the temperature regulating component with a magnitude that undergoes an abrupt change. Then, during a time interval that begins with the abrupt change in thermal power, a temperature change is sensed in either the temperature regulating component, or the chip. Thereafter, electrical power is applied to the chip in the tester only if the temperature change, which is sensed by the sensing step, meets a predetermined criteria.

Abstract: Leakage power consumed by an integrated circuit is estimated as the difference between total power consumption and a nominal expected power consumption. Leakage power is reduced by cooling the integrated circuit in an active cooling system. By expending power in the active cooling system, the integrated circuit is cooled and the total power consumption is decreased. When the decrease in total power consumption is greater than the power expended in the cooling system, an overall power savings is achieved.

Abstract: An output terminal is provided at the middle point of each of output windings 112X and 112Y of a resolver 10. A difference between a voltage V2X (V2Y), between one of the end terminals and the middle point of the output winding, and a voltage V1X (V1Y), between the other end terminal and the middle point of the output winding, is detected by a difference voltage detection circuit 101, and supplied to a logical summing circuit 126 via a rectifier circuit 124 and a comparator circuit 125. In accordance with an output from the logical summing circuit 126, a fault of the windings, such as short-circuiting or the like, can be detected even at a specific rotation angle of the rotor. Thus, a resolver in which a fault thereof can be easily detected, as well as a resolver fault detection circuit, can be provided.

Abstract: One end of an inductor is connected to a drain of a P-channel type MOS transistor. A source of source of MOS transistor is connected to an electric power source which supplies a voltage Vdd. The other end of inductor is connected via a dummy capacitor to a ground. Furthermore, a dummy resistor is connected between a drain of MOS transistor and the ground. The dummy resistor has the same resistance as that of a parasitic resistor existing between the inductor and the MOS transistor. Another dummy capacitor is connected between the dummy resistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground. A current measuring device is connected between a source of MOS transistor and the ground.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: A method and apparatus for handling small semiconductor devices in the testing of these devices. Multiple devices are mounted within a device strip carrier and are positioned in the testing position. This positioning of the device strip carriers is performed using device strip carrier alignment tools; the device strip carrier can readily be repositioned with respect to the test head/probe card for testing of multiple devices contained within the device strip carrier.

Abstract: A system (10) for and method of testing a device under test (DUT) (12) having a plurality of probe pads (14) utilizing a dual probe technique to overcome contact resistance that may be present. The system comprises a plurality of sensing probes (30) and a plurality of forcing probes (32) arranged in pairs consisting of one sensing probe and one forcing probe. Each pair of sensing and forcing probes is provided for contacting one of the probe pads on the DUT. Each forcing probe is in electrical communication with a power supply (20) via a switching matrix (24), and each sensing probe is in electrical communication with a voltage meter (52) via the switching matrix. During testing, at least one of the power supplies provides a voltage to a corresponding forcing probe in contact with a particular probe pad.