Abstract: Method for reducing memory fragmentation characterized in that it the steps of: for each image in a source set of images (601) determining image size (602) in pixels and obtaining (603) a minimal total number of pixels for an aggregated surface by obtaining a sum of image sizes; factorizing (604) the sum of image sizes into a surface's width and height; allocating memory (702) for the surface (701); creating (703) a mapping between an image identifier and its location, width, height for each image associated with the surface; for each image, according to its offset in the surface, the two-dimensional space of the image is cast (704) to one dimension; knowing the casting formula between the one and two-dimensional spaces, copying each image to the surface (705).

Abstract: A data temporary storage apparatus includes a moving unit coupled to a first storage unit and multiple second storage units. The moving unit receives a moving instruction having contents including a read address, a destination address and a predetermined moving rule. The moving unit further executes the moving instruction to fetch input data by row from the first storage unit according to the read address, and to temporarily stores one after another in an alternate and sequential manner the data in each row to each of the second storage units indicated by the destination address. The data moving, data reading and convolution approaches of the present invention implement in parallel data moving and a convolution operation, achieving a ping-pong operation of convolution units and enhancing convolution efficiency, while reducing memory costs since configuring two data storage spaces in a memory is not necessary.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. For example, the computing device monitors storage unit (SU)-based write transfer rates and SU-based write failure rates associated with each of the SUs for a write request of encoded data slices (EDSs) to the SUs within the DSN. The computing device generates and maintains a SU write performance distribution based on monitoring of the SU-based write transfer rates and the SU-based write failure rates and adaptively adjusts a trimmed write threshold number of EDSs and/or a target width of EDSs for write requests of sets of EDSs to the SUs within the DSN.

Abstract: According to one embodiment, an information processing device includes a characteristics monitoring unit, a determination unit, and a notification unit. The characteristics monitoring unit monitors characteristics information that indicates at least one of its performance and lifetime with respect to a storage device, and includes input/output characteristics. The determination unit determines, based on monitored characteristics information including the input/output characteristics, whether change instruction for changing characteristics is to be notified to the storage device. The notification unit notifies the storage device of the change instruction when the determination unit determines that the change instruction is to be notified.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first parity data for the first command is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first parity data is copied from the RAM1 to a parking section in the storage unit, and second parity data associated with the second zone is copied from the parking section to the RAM1. The second parity data is then updated in the RAM1 with the data of the second command and copied to the parking section.

Abstract: Example distributed storage systems, controller nodes, and methods provide hierarchical blacklisting of storage system components in response to failed storage requests. Storage elements are accessible through hierarchical storage paths traversing multiple system components. Blacklisted components are aggregated and evaluated against a hierarchy threshold at each level of the hierarchy and all components below the component are blacklisted if the hierarchy threshold is met. Blacklisted components are avoided during subsequent storage requests.

Abstract: Techniques perform data storage. Such techniques may involve writing metadata to a first cache of a first processor, the metadata indicating allocation of a storage resource to user data. Such techniques may further involve determining an address range of the metadata in the first cache. Such techniques may further involve copying only data stored in the address range in the first cache to a second cache of a second processor. Accordingly, the data transmission volume between two processors is reduced, which helps to improve the overall performance of a storage system.

Abstract: Provided herein may be a memory controller configured to control a memory device. The memory controller may include: a mapping data determination unit configured to receive, from a memory device, bitmap information indicating whether a map segment, corresponding a bit included in the bitmap information and including a plurality of pieces of extended mapping data, has been stored in the memory device and a mapping data management unit configured to output information about generation of the plurality of pieces of extended mapping data based on the bitmap information. Each of the plurality of pieces of extended mapping data may include mapping information between a logical block address and a physical block address.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device configured to include a plurality of memory blocks and copy data from victim blocks among the plurality of memory blocks into a target memory block during a garbage collection operation, and a memory controller configured to control the memory device to perform the garbage collection operation, and configured to control the memory device, during the garbage collection operation, to erase the data stored in the victim blocks using a multi-erase method.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory storage to store data, a volatile memory storage, and a host interface layer to receive requests from a host machine. An SSD controller may manage reading data from and writing data to the flash memory storage, with a flash translation layer to translate between Logical Block Addresses and Physical Block Addresses, a flash memory controller to access the flash memory storage, a volatile memory controller to access the volatile memory storage, and an orchestrator to send instructions to a Data Movement Interconnect (DMI). The DMI may include at least two kernels, a Buffer Manager, a plurality of ring agents associated with the kernels and the Buffer Manager to handle messaging, a Data Movement Manager (DMM) to manage data movement, at least two data rings to move data between the ring agents, and a control ring to share commands and acknowledgments between the ring agents and the DMM.

Abstract: Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device receiving a first read instruction from a host process. The first read instruction includes a namespace offset. A first logical address is generated by combining a namespace identifier for the namespace assigned to the host process and the namespace offset. The first logical address is translated into a first physical address using a plurality of hierarchical tables. A second read instruction, which includes the first physical address and the first logical address, is generated. The second read instruction is sent to a memory component. The memory component validates the translation of the first logical address by comparing the first logical address in the second read instruction to metadata associated with data to be read at the first physical address.

Abstract: The disclosure provides an approach for testing if a cache line of a cache has been flushed to non-volatile memory (NVM). The approach generally includes reading, by a central processing unit (CPU), data from the NVM. The approach further includes storing, by the CPU, a copy of the data in the cache as a cache line. The approach further includes modifying, by the CPU, at least a portion of the copy of the data in the cache. The approach further includes requesting, by the CPU, the cache line be flushed to the NVM. The approach further includes performing, by the CPU, one or more instructions in parallel to the cache line being flushed to the NVM. The approach further includes requesting, by the CPU, a state of the cache line and determining if the cache line has been persisted in the NVM based on the state of the cache line.

Abstract: Provided is an operation method of a controller which controls a memory device. The operation method may include: determining a caching order of plural pieces of map data included in a request map segment including request map data; requesting the request map segment from the memory device; marking data in a marking region which is determined based on the caching order; caching, in the caching order, the plural pieces of map data read from the memory device; and acquiring the request map data from the cached data, depending on whether the data stored in the marking region is changed.

Abstract: Various embodiments are provided for managing multiport banked memory arrays in a computing system by a processor. One or more conflicts may be eliminated in a multiport banked memory array upon receiving one or more write operations, read operations, or a combination thereof according to a selected priority and access protocol.

Abstract: Techniques for performing cache management includes partitioning entries of a hash table into buckets, wherein each of the buckets includes a portion of the entries of the hash table, configuring a cache, wherein the configuring includes allocating a section of the cache for exclusive use by each bucket, and performing first processing that stores a data block in the cache. The first processing includes determining a hash value for a data block, selecting, in accordance with the hash value, a first bucket of the plurality of buckets, wherein a first section of the cache is used exclusively for storing cached data blocks of the first bucket, storing metadata used in connection with caching the data block in a first entry of the first bucket, and storing the data block in a first cache location of the first section of the cache.

Abstract: A method and a system for data migration on a multi-tiered storage system are provided. The method can include receiving a migration task indicating a dataset to migrate. The method can further include building a plurality of buffers onto at least one high-performance storage tier. The high-performance storage tier can be based on the read speed of that tier. The method can also include referencing a shadow mapping to locate physical data from the dataset stored on a first buffer. The method can include migrating the physical data from the first buffer to a migration destination. The method can further include deallocating the first buffer. The deallocation can allow allocation of additional physical data onto the first buffer for migration.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving an unmap command, the unmap command identifying a first logical extent located in a higher storage tier of a multi-tiered data storage system having the higher storage tier and a lower storage tier, sending an instruction to unmap the first logical extent from the higher storage tier, sending an instruction to decrement a heat associated with the unmapped first logical extent in response to sending the instruction to unmap the first logical extent, sending an instruction to remove the unmapped first logical extent from the higher storage tier, selecting, using a heat map, at least one second logical extent located in the lower storage tier for promotion to the higher storage tier, and sending an instruction to relocate the at least one second logical extent from the lower storage tier to the higher storage tier.

Abstract: A memory device having a memory array with a plurality of memory addresses and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each of the d rows corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a first memory address of the plurality of memory addresses and to hash the first memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured to adjust, for each of the d sketch locations, a stored sketch value by a first amount corresponding to the event.

Abstract: A memory device having a memory array and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each row corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a memory address and to hash the memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured, for each of the d sketch locations, to set a detection window flag, if it is not already set, and to adjust a stored sketch value by an amount corresponding to the event. The controller is also configured to evaluate a summary metric corresponding to the stored sketch value in each of the d sketch locations to determine if a threshold value has been reached.

Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for setting a termination condition of a garbage collection operation based on an over-provisioning ratio of the nonvolatile memory device, performing the garbage collection operation, and terminating the garbage collection operation according to the termination condition.