Abstract: The invention relates to a mixer for generating an analog output signal XOUT from an analog input signal XIN using a mixing signal having a mixing frequency fMIX, the mixer comprising: a scaler being configured to sample the analog input signal XIN at a plurality of discrete points in time k with a sampling frequency fS to obtain a sampled analog input signal XIN[k] having a continuous signal value, and to generate the analog output signal XOUT having a continuous signal value by scaling the sampled analog input signal XIN[k] on the basis of a plurality of scaling coefficients A[k], wherein the scaling coefficients A[k] are a time-discrete representation of the mixing signal.

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin on the chip, and where the pin is adapted to be coupled to an external resistor, where the external resistor is external to the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first switch, and a second capacitor coupled to a second switch. The oscillator circuit includes leakage circuitry coupled to the current mirror, where the leakage circuitry is configured to draw a current from the current mirror proportional to a leakage current flowing through the external resistor from circuitry internal to the chip.

Abstract: A power supply system comprises a portable first power supply device and second power supply device. The portable first power supply device has a handle to be gripped by a hand of a user. A supply unit of the portable first power supply comprises an inverter circuit which converts at least a portion of excess power into an alternating current, and supplies to the second power supply device via a second connection unit and a power line, power of the alternating current outputted from the inverter circuit.

Abstract: In a power supply system, a control device is configured to adjust a state of charge of each of an alternating-current battery string and a direct-current battery string by power transfer between the alternating-current battery string and the direct-current battery string before performing requested energy management.

Abstract: An electric power supply system includes an alternating current electric power supply circuit that converts direct current electric power of a first direct current sweep unit including a battery string into alternating current electric power using a first inverter and outputs it, and an alternating current sweep unit that includes a U-phase battery string, a V-phase battery string, and a W-phase battery string that are Y-connected. Output densities of batteries of the battery string are higher than output densities of batteries of the alternating current sweep unit. Alternating current electric power is output from the alternating current sweep unit and the alternating current electric power supply circuit, and after a predetermined period elapses, the output of the alternating current electric power from the alternating current electric power supply circuit is stopped.

Abstract: A bandgap reference circuit includes a reference current generation circuit configured to output a bandgap reference current insensitive to a temperature change, by using a first voltage inversely proportional to temperature and a third voltage proportional to temperature. The third voltage is a difference between the first voltage and a second voltage. The bandgap reference circuit further includes a resistivity temperature coefficient cancellation circuit configured to remove a first current proportional to temperature from the bandgap reference current by using the third voltage, and a reference voltage generation circuit configured to output a bandgap reference voltage insensitive to a temperature change by using a second current inversely proportional to temperature and a first resistance proportional to temperature. The second current is generated by removing the first current from the bandgap reference current.

Abstract: A voltage-controlled oscillator analog-to-digital converter (VCO-ADC) includes a first source follower coupled between a first input terminal and a first internal node; a first VCO having an input coupled to a second internal node; a first variable resistor coupled between the first internal node and the second internal node; and a digital signal processing component coupled between an output of the first VCO and a output terminal.

Abstract: A transposed delay line oscillator including a mode selection filter and a transposed delay line is provided. An output of the transposed delay line is coupled to an input of the mode selection filter to establish an oscillator loop. Based on the transposed delay line output, the mode selection filter generates a mode selection signal including an isolated oscillatory mode, in a Radio Frequency (RF) band. The transposed delay line receives the mode selection signal for transposition to an intermediate frequency of an intermediate frequency (IF) delay line. The IF delay line includes a delay filter and a phase noise suppression loop configured to suppress de-correlated transposition phase noise resulting from a delay of the delay filter. Suppression of phase noise in the IF delay line enables cancellation of transposition phase noise when transposing the IF delay line output to the RF band.

Abstract: A power conversion device converts a direct-current power on the DC side of the power conversion device to an alternating-current power by an inverter circuit having a plurality of semiconductor switching elements, and outputs the AC power from the AC side of the power conversion device. A current detector detects a reactor current output from the inverter circuit. As overcurrent detector detects overcurrent in a control mode in which the reactor current is caused to follow a reactor current command value, control circuit starts an overcurrent mode in which a time period where the reactor current monotonically decreases is provided. In the overcurrent mode, whether to switch the overcurrent mode to the normal control mode is determined based on the reactor current or in accordance with a timing corresponding to a zero-cross point of a voltage or current on the AC side.

Abstract: An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.

Abstract: In an embodiment, an integrated circuit die includes a semiconductor substrate, patterned metal layers compiled over the semiconductor substrate, and a tapered multipath inductor formed in the patterned metal layers. The tapered multipath inductor includes, in turn, an inductor input terminal, an inductor output terminal, and N number of parallel inductor tracks electrically coupled between the inductor input terminal and the inductor output terminal. The parallel inductor tracks wind or wrap around an inductor centerline to define a plurality of multipath inductor windings including an innermost winding and an outermost winding. The parallel inductor tracks further vary in track width when progressing from the outermost winding to the innermost winding of the plurality of multipath inductor windings.

Abstract: A physics cell includes a sealed glass vial that contains a high-purity dipolar gas (e.g., OCS) at a low pressure (e.g., between about 0.01 millibar and 0.2 millibar). The vial can be sealed using a laser cutting process that involves only local heating of the vial that does not denature the bulk of the contained gas. One or more electromagnetically translucent windows or vial-end access points provide access to electromagnetic waves launched or received by one or more electromagnetic antennas at a frequency that is adjusted to match the quantum transition frequency of the gas based on a detected maximum absorption frequency. The glass-vial physics cell can be fabricated at lower cost than physics cells fabricated from bonded wafers. Multiple vials can be joined by a waveguide in an enclosure so that launch and receive antennas can be provided at a single end of the vials.

Abstract: A power supply system that outputs AC power to an object to which power is to be supplied includes: a first power supply circuit including a DC battery string and an inverter and configured to output first AC power; a second power supply circuit including an AC battery string and configured to output second AC power; and a control device. In the first mode, power is transferred between the object and the second power supply circuit. In the second mode, power is transferred between the object and each of the first and second power supply circuits. The control device starts supplying the second AC power to the object in the first mode, and when a power supply current becomes larger than a first threshold, supply the first and second AC power to the object in the second mode.

Abstract: Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

Abstract: A disclosed circuit arrangement detects the supply voltage level to the “device” (SoC, chip, SiP, etc.) and adjusts bias voltages to receiver and transmitter circuits of the device to levels suitable for the device in response to the supply voltage ramping-up during a power-on reset (“POR”) sequence. The circuitry holds the receiver output at a constant logic value while the supply voltage is ramping up and the POR signal is asserted. The disclosed circuitry also protects the transceiver as the voltage domain of the input signal is unknown and the voltage between any two terminals of a transistor of the transceiver cannot exceed a certain level.

Abstract: Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.

Abstract: An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

Abstract: A transposed delay line oscillator including a mode selection filter and a transposed delay line is provided. An output of the transposed delay line is coupled to an input of the mode selection filter to establish an oscillator loop. Based on the transposed delay line output, the mode selection filter generates a mode selection signal including an isolated oscillatory mode, in a Radio Frequency (RF) band. The transposed delay line receives the mode selection signal for transposition to an intermediate frequency of an intermediate frequency (IF) delay line. The IF delay line includes a delay filter and a phase noise suppression loop configured to suppress de-correlated transposition phase noise resulting from a delay of the delay filter. Suppression of phase noise in the IF delay line enables cancellation of transposition phase noise when transposing the IF delay line output to the RF band.

Abstract: A power system including a power converter system and an electric machine is provided. In one aspect, the power converter system has first and second switching elements. The electric machine includes a first multiphase winding electrically coupled with the first switching elements and a second multiphase winding electrically coupled with the second switching elements. The first and second multiphase windings are arranged and configured to operate electrically opposite in phase with respect to one another. One or more processors control the first switching elements to generate first pulse width modulated (PWM) signals based on received voltage commands to render a first common mode signal and also control the second switching elements to generate second PWM signals based on received voltage commands to render a second common mode signal. The rendered first and second common mode signals have the same or similar waveform with opposite polarity with respect to one another.

Abstract: Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.