Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidised sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidised sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

Abstract: A pulse sample demodulator which has a first sample and hold circuit detects the peak amplitude of the time varying waveform during a short sampling interval. The first sample and hold circuit is triggered by narrow pulses produced by a circuit responsive to the occurrence of each peak in the time varying waveform. A second sample and hold circuit, sampling during an interval not coincident with the first sampling interval, receives the information stored in the first sample and hold circuit; but sampling at a different interval, it does not receive the time varying signal applied to the first sample and hold circuit, which would otherwise appear as ripple in the output of the demodulator.

Abstract: A C-MOS oscillator circuit having input and output terminals adapted to be connected to a resonator and two active MOS transistors of complementary types connected in series between the supply terminals of the circuit, which supply terminals are connected to the positive and negative poles of a source of d.c. voltage, the sources of the transistors being connected to a supply terminal and the drains being connected to the output terminal. The d.c. bias and the a.c. voltage control of each of the active transistors are ensured by a MOS transistor of the same type connected as a diode between its gate and its drain, a current source connected between its gate and the supply terminal to which the source of the other active transistor is connected, and a capacitive voltage divider which is connected between the supply terminal, to which its source is connected, and the input terminal, and the intermediate point of which is connected to its gate.