Abstract: A method for monitoring overlay alignment on a wafer that includes identifying a target machine, identifying a target process, identifying a plurality of critical layers, obtaining a plurality of overlay data from at least one of designated registration patterns on the wafer as baseline data, providing a plurality of reference overlay data, correlating the plurality of the reference overlay data with the baseline data to obtain overlay error, comparing the overlay error with specifications of the target machine, accepting the baseline data when the overlay error is within the specifications, and performing overlay alignment monitoring with the baseline data.

Abstract: A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.

Abstract: A processor is configured to detect a branch instruction have a forward branch target address within a predetermined range of the branch fetch address of the branch instruction. If the branch instruction is predicted taken, instead of canceling subsequent instructions and fetching the branch target address, the processor allows sequential fetching to continue and selectively cancels the sequential instructions which are not part of the predicted instruction sequence (i.e. the instructions between the predicted taken branch instruction and the target instruction identified by the forward branch target address). Instructions within the predicted instruction sequence which may already have been fetched prior to predicting the branch instruction taken may be retained within the pipeline of the processor, and yet subsequent instructions may be fetched.

Abstract: A data processing apparatus has a basic processing unit (BPU) 2, a channel processor (CHP) 10, message channel units (MCH) 11n, message channel receivers (MCHR) 6m connected respectively to the message channel units 11n, and a structured external storage device (SES) 6 which may be connected to a plurality of hosts via the message channel receivers 6m and which includes a cache memory 8 for accommodating data shared by the hosts. Before issuing a synchronous instruction, a program issues an instruction notifying in advance the inventive apparatus of the intended use of hardware resources. When the hardware resources are reserved by the notifying instruction, the apparatus guarantees the subsequent execution of the synchronous instruction. Because synchronous instructions are always carried out, the system overhead is lowered.

Abstract: A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of translation units, a future file, a central window, a plurality of functional units, a result queue, and a plurality of physical registers. The floating point unit receives speculative instructions, decodes them, and then stores them in the central window. Speculative top of stack values are generated for each instruction during decoding. Top of stack relative operands are computed to physical registers using a register map. Register stack exchange operations are performed during decoding. Instructions are then stored in the central window, which selects the oldest stored instructions to be issued to each functional pipeline and issues them. Conversion units convert the instruction's operands to an internal format, and normalization units detect and normalize any denormal operands.

Abstract: A processor architecture with an instruction set having a predict instruction, the predict instruction providing static prediction information and a statically predicted target address to the processor for a branch instruction. The processor decodes a predict instruction to obtain an associated pair of addresses comprising a predicted target address and a referenced instruction address, and fetches a predicted target instruction having an instruction address matching the predicted target address when a fetched and decoded branch instruction has an instruction address matching the referenced instruction address.