Patents Examined by Sam Dillon
  • Patent number: 7996623
    Abstract: Method and apparatus for managing the storage of data in a cache memory by placing pending read requests for sequential data in a dedicated read ahead stream control (RASC) data structure, and further configured for dynamically switching both ways, in response to data stored in the RASC, between speculative non-requested read ahead data streaming to read behind stream locking on the read requests in the RASC.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: August 9, 2011
    Assignee: Seagate Technology LLC
    Inventor: Michael D. Walker
  • Patent number: 7421538
    Abstract: A storage control apparatus controls physical disks according to the host access using a pair of controllers, while mirroring processing is decreased when data is written to a cache memory and high-speed operation is enabled. The mirror management table is created with allocating the mirror area of the cache memory of the other controller, and acquisition of a mirror page of the cache memory of the other controller is executed referring to the mirror management table without an exchange of mirror page acquisition messages between the controllers.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: September 2, 2008
    Assignee: Fujitsu Limited
    Inventors: Joichi Bita, Daiya Nakamura
  • Patent number: 7406565
    Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous processor execution state corresponding to an instruction associated with the speculative fill. The backup system may initiate a backup of the processor pipeline to the previous processor execution state if the speculative fill is determined to be non-coherent, and the processor pipeline may continue execution of program instructions if the speculative fill is determined to be coherent.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: July 29, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney
  • Patent number: 7383409
    Abstract: One disclosed embodiment is a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request. The multi-processor system can further comprise a non-retired store cache that retains non-retired store data based on program instructions to store data into a data cache associated with the processor. The non-retired store data can be written to the data cache if data of a speculative fill associated with the non-retired store data is determined to be coherent. Other apparatus and methodologies are disclosed.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: June 3, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney
  • Patent number: 7376794
    Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source request by the source processor, and a coherent signal generated by the multi-processor system that provides an indication of which data fill of the at least one data fill is a coherent data fill.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: May 20, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney, Stephen R. Van Doren
  • Patent number: 7340565
    Abstract: Multiprocessor systems and methods are disclosed. One embodiment may comprise a plurality of processor cores. A given processor core may be operative to generate a request for desired data in response to a cache miss at a local cache. A shared cache structure may provide at least one speculative data fill and a coherent data fill of the desired data to at least one of the plurality of processor cores in response to a request from the at least one processor core. A processor scoreboard arbitrates the requests for the desired data. A speculative data fill of the desired data is provided to the at least one processor core. The coherent data fill of the desired data may be provided to the at least one processor core in a determined order.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: March 4, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney
  • Patent number: 7328314
    Abstract: An instruction memory shared by a number of processing units has a plurality of individually accessible sections. A software program in the instruction memory is distributed among the memory sections. Sequential parts of the software program are in sequential sections. The software program may have a common portion which is repeated in each of the memory sections. Arbiter logic may control which of the processing units accesses which of the memory sections in each memory access cycle.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: February 5, 2008
    Assignee: Alcatel-Lucent Canada Inc.
    Inventors: Chad Kendall, Predrag Kostic, Robert Elliott Robotham
  • Patent number: 7325110
    Abstract: In a storage switch to control a snapshot operation in the file unit, the delay in the writing operation of a host due to a data saving operation is prevented. In a snapshot acquiring method, the memory usage in a switch is reduced to create a snapshot. The storage switch includes a function to create a snapshot of a file. To prevent occurrence of delay due to the data saving operation, a mirror of source data as a snapshot target is kept in a source volume in any situation or according to a predetermined condition with synchronization established between the mirror and the source data. In the creation of the snapshot, the mirror data is used. By creating the mirror data in sequential positions in the source volume, the positional correspondence between the source side and the snapshot side is simplified.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: January 29, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kei Kubo, Koji Sugiyama
  • Patent number: 7127553
    Abstract: A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: October 24, 2006
    Assignee: Infineon Technologies AG
    Inventors: Alexander Benedix, Georg Braun, Bernd Klehn