Abstract: In a mailing system including a postage value determining system processor which communicates along parallel channels and peripheral subsystem processors adapted to communicate with a system processor along a serial data bus, an interface is provided between the system processor and the serial bus. The interface includes a first and a second communications processor. The first processor is programmed to communicate with the system processor and with the second communications processor. The second communications processor is programmed to communicate with the first processor and with peripheral subsystem processors through the serial bus. Data and control signals are transmitted between the communications processors through an interprocessor channel. The interprocessor channel includes lines connected to reference voltage levels for providing appropriate signal levels for recognition by the communications processors which operate on different voltage signal levels.

Abstract: A digital signal processor has timing means for providing a succession of sample intervals in which incoming digital signals may have discrete values (e(o)). A serial delay such as a multi or single bit shift register progressively delays a digital signal giving a delayed signal (e(m)). An arithmetic section has a plurality of elements such as multi or single bit multipliers, or difference squares. Each element operates on non delayed signals (e(o)) and signals (e(m)) from an associated stage of the delay. An accumulating store has a plurality of channels each associated with and arithmetic element. Collectively the channels provide the required mathematical operation, e.g. auto or cross correlation function or structure function calculation. The interval of delay between channels is arranged to increase substantially geometrically e.g. by .sqroot.2. The overall delay increase may be variable and geometric although increases between adjacent channels may be approximations to a geometric increase.

Abstract: The present invention is a multiprocessor machine control system in which the failure of one of the processors to reset can be ignored by the rest of the control system. In particular, a software crash or other abnormality on one of the processors will generate a reset procedure. If the processor cannot be reset, this will indicate a processor board failure such as a hardware failure. If the processor and its controlled elements are not crucial to the machine operation, then the control wll ignore the failed processor as though it were not in the control system, and continue with machine operation.

Abstract: In a mailing system including a postage value determining system processor which communicates along parallel channels and peripheral subsystem processors adapted to communicate with a system processor along a serial data bus, an interface is provided between the system processor and the serial bus. The interface includes a first and a second communications processor. The first processor is programmed to communicate with the system processor and with the second communications processor. The second communications processor is programmed to communicate with the first processor and with peripheral subsystem processors through the serial bus. Data and control signals are transmitted between the communications processors through an interprocessor channel. The interprocessor channel includes lines connected to reference voltage levels for providing appropriate signal levels for recognition by the communications processors which operate on different voltage signal levels.

Abstract: A microprocessor is disclosed having a bus controller which is capable of automatically performing multiple bus cycles in response to a multi-cycle signal received from the control unit. The bus controller includes means for automatically incrementing the access address provided by the control unit, and for controlling the transfer of the data between the bus and respective destinations in the control units.