Abstract: In one aspect, the present invention teaches a multiple-gate transistor 130 that includes a semiconductor fin 134 formed in a portion of a bulk semiconductor substrate 132. A gate dielectric 144 overlies a portion of the semiconductor fin 134 and a gate electrode 146 overlies the gate dielectric 144. A source region 138 and a drain region 140 are formed in the semiconductor fin 134 oppositely adjacent the gate electrode 144. In the preferred embodiment, the bottom surface 150 of the gate electrode 146 is lower than either the source-substrate junction 154 or the drain-substrate junction 152.

Abstract: A ferroelectric capacitor including a bottom electrode which has a projecting portion, a top electrode, a ferroelectric layer and a dielectric layer formed between the bottom electrode and the top electrode. The dielectric layer is formed on a peripheral area of the bottom electrode. The ferroelectric layer is formed on the dielectric layer and on the projecting portion of the bottom electrode. As a result, a damaged layer which is formed during an etching process occurs at the ineffective area of the ferroelectric capacitor.