Abstract: Described are methods and systems for dynamically reallocating memory amongst virtual machines executing within a virtualization environment. A computer can execute a virtualization environment that can include one or more virtual machines and that can include a memory manager. The memory manager can dynamically reallocate memory by identifying a maximum and minimum memory value for each virtual machine, determining a target memory value for each virtual machine using the maximum and minimum memory value, and identifying one or more virtual machines that have an actual memory usage value that is less than the target memory value calculated for those virtual machines. To re-allocate the memory, the memory manager can allocate additional memory to the identified virtual machines by inflating a balloon driver, then de-allocate the additional memory, and reallocate the de-allocated, additional memory to other virtual machines within the virtualization environment.

Abstract: A non-volatile memory access method and system, and a non-volatile memory controller are provided for accessing a plurality of physical blocks in a non-volatile memory chip, and each physical block has a plurality of physical pages. The method includes determining whether there is enough space in a first physical block to write a plurality of specific physical pages when data stored in one of the specific physical pages are to be updated; and writing valid data and data to be updated into the first physical block when the first physical block has enough space to write the specific physical pages.

Abstract: A method is provided that includes performing first and second exclusive activation checks separately on first and second storage units, respectively, with a node using a software RAID function and activating a RAID disk with the first storage unit and the second storage unit using the software RAID function in response to the first and the second exclusive activation checks indicating that the first and the second storage units, respectively, can be activated as the RAID disk by the node.

Abstract: According to one embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising: computer readable program code configured to receive a mount request to access at least one host data record on a virtual tape storage (VTS) system; computer readable program code configured to determine a number of host compressed data records per physical block on a magnetic tape medium; computer readable program code configured to determine a physical block ID (PBID) that corresponds to the requested at least one host data record; computer readable program code configured to access a physical block on the magnetic tape medium corresponding to the PBID; and computer readable program code configured to output the physical block without outputting an entire logical volume from the magnetic tape medium that the physical block is stored to. Other systems and computer program products are also described.

Abstract: Method and apparatus for optimally placing memory devices within a computer system. A memory controller may include circuitry configured to retrieve or one or more performance metrics a plurality of memory devices connected thereto. Based on the performance metrics and one or more predefined rules for placing memory devices, the circuitry may determine an optimal placement of the memory devices in the system.

Abstract: A method and system for simulating in software a digital computer system by performing virtual to physical translations of simulated instructions is disclosed. The number of virtual to physical translations using hash lookups is reduced by analyzing sequences of the instructions for determining with high probability whether the memory accesses made by the instructions perform the same virtual to physical translation in order to reduce the number of necessary hash lookups to enable faster simulation performance.

Abstract: A system and method for concurrency control may use slotted read-write locks. A slotted read-write lock is a lock data structure associated with a shared memory area, wherein the slotted read-write lock indicates whether any thread has a read-lock and/or a write-lock for the shared memory area. Multiple threads may concurrently have the read-lock but only one thread can have the write-lock at any given time. The slotted read-write lock comprises multiple slots, each associated with a single thread. To acquire the slotted read-write lock for reading, a thread assigned to a slot performs a store operation to the slot and then attempts to determine that no other thread holds the slotted read-write lock for writing. To acquire the slotted read-write lock for writing, a thread assigned to a slot sets its write-bit and then attempts to determine that the write-lock is not held.

Abstract: Provided is a computer system including: a host computer; a first storage system connected to the host computer; and a second storage system connected to the first storage system; in which the first storage system sets a first logical volume recognized by the host computer as a logical storage area; the first logical volume includes a plurality of first storage areas; a first real storage area on the first disk drive is allocated to at least one of the first storage areas. In the computer system, the second storage system sets a second logical volume corresponding to the first logical volume, and the first storage system transmits data stored in the first storage area allocated to the first storage area to the second storage system when the first real storage area is allocated to the first storage area.

Abstract: When a thread begins an atomic transaction, the thread reads one or more variables from one or more source addresses. The read portion of the transaction is constrained to a predetermined amount of time or number of cycles (N). The mechanism then performs a test and set operation to determine whether any other threads hold locks on the one or more source addresses. If the locks for the one or more source addresses are free, then the thread acquires locks on the one or more source addresses. The thread then performs work and updates the one or more variables. Thereafter, the mechanism delays for an amount of time or number of cycles greater than or equal to N before releasing the locks. If another thread attempts to acquire a lock on the one or more source addresses, then the test and set operation for that other thread will fail.

Abstract: A method and system for backing up and restoring data in a file system that includes junctions is provided. In a backup operation, a junction is encoded as a symbolic link (“symlink”) directive, and sent with a sequential image data stream in the backup operation and written to a tape or disk. In a restore operation, when the encoded symlink directive is encountered after data is read from the tape, the symlink is decoded by an administrator to obtain the embedded junction information contained in the symlink directive. The administrator can then recreate the junction using the information. The junction information is thereby transmitted as part of the backup and restore operation while remaining transparent to third party software performing the backup and restore processes.

Abstract: A device and method is provided for commonly and securely allowing, as access control on a memory card, a plurality of information processing apparatuses to lock/unlock the memory. On the basis of a lock command input from an information processing apparatus serving as a host, such as a PC, an information storage device, such as a memory card, determines whether (a) a standard lock key set serving as a key set prohibiting output or (b) an export lock key set serving as a key set permitting output is detected and stores corresponding key set information. Only when the export lock key set is detected, output is permitted provided that predetermined verification succeeds.

Abstract: A method and apparatus for configuring a memory device, such as a flash memory device, is herein described. Features/functional modules of a memory device, are selectable by a manufacturer, customer, or user. Instead of a manufacturer having to complete numerous redesigns of a memory product to meet multiple customer's special needs, a single all inclusive device is manufactured and the customized features are selected/configured, by the manufacturer, or by the customer themselves. By using one time programmable (OTP) flags, the features are enabled or disabled, by the manufacturer, customer, or user, and may potentially not be altered by a user later. Moreover, after configuring a memory device, a manufacturer, customer, or end user may also lock down a configuration module to ensure the configuration itself is not later intentionally or inadvertently altered.

Abstract: Described embodiments provide a media controller that synchronizes data cached in a buffer and corresponding data stored in one or more sectors of a storage device. A buffer layer module of the media controller caches data transferred between the buffer and the storage device. One or more contiguous sectors are associated with one or more chunks. The buffer layer module updates a status corresponding to each chunk of the cached data and scans the status corresponding to a first chunk of cached data. If, based on the status, the first chunk of cached data is more recent than the corresponding data stored on the storage device, a media layer module synchronizes the data on the storage device with the cached data. The status corresponding to the group of one or more sectors is updated. The media layer module scans a next chunk of cached data, if present.

Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

Abstract: Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.

Abstract: Described embodiments provide a method of transferring, by a media controller, data associated with a host data transfer between a host device and a storage media. A buffer layer module of the media controller segments the host data transfer into one or more data transfer segments. Each data transfer segment corresponds to at least a portion of the data. The buffer layer module allocates a number of physical buffers to a virtual circular buffer for buffering the one or more data transfer segments. The buffer layer module transfers, by the virtual circular buffer, each of the data transfer segments between the host device and the storage media through the allocated physical buffers.

Abstract: One embodiment of the present invention provides a system that uses versioned pointers to facilitate reusing memory without having to reclaim the objects solely through garbage collection. The system operates by first receiving a request to allocate an object. Next, the system obtains the object from a pool of free objects, and sets an allocated/free flag in the object to indicate that the object is allocated. The system also increments a version number in the object, and also encodes the version number into a pointer for the object. The system then returns the pointer, which includes the encoded version number. In this way, subsequent accesses to the object through the pointer can compare the version number encoded in the pointer with the version number in the object to determine whether the object has been reused since the pointer was generated.

Abstract: The present invention provides a system, method, and computer program product for “cooling” selected disks in a set of disks connected to a storage system by reducing access frequency to the selected disks and pausing the disks with the reduced access frequency. Pausing some disks advantageously reduces power consumption by the disks.

Abstract: At least one processor for executing a plurality of programs, a storage area which is capable of storing an information element temporarily, and a storage device which is capable of storing the information element, are provided. A certain level of importance is associated with each of the programs themselves or a performance requirement of each program. When a certain information element is output as a result of execution of a certain program from among the plurality of programs, the certain information element is written into the storage area. Then, a plurality of information elements written in the storage area is output to the storage device side in order of precedence from the information element of the executed program, or the performance requirement thereof, having the highest level of importance.

Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system including a processor that executes program instructions across at least one memory barrier. A request engine may provide an updated data fill corresponding to an invalid cache line. The invalid cache line may be associated with at least one executed load instruction. A load compare component may compare the invalid cache line to the updated data fill to evaluate the consistency of the at least one executed load instruction.