Abstract: A manufacturing method of a memory includes: providing a substrate and a bit line contact layer; forming a dummy bit line structure on top of the bit line contact layer; forming a spacer layer on the sidewall of both the dummy bit line structure and the bit line contact layer; forming a dielectric layer on the sidewall of the spacer layer; forming a sacrificial layer filling the area between adjacent dummy bit line structures, wherein the sacrificial layer covers the sidewall of the dielectric layer; after the sacrificial layer is formed, removing the dummy bit line structure; forming a bit line conductive portion which fills the hole and covers the bit line contact layer; and, after the bit line conductive portion is formed, removing the spacer layer.

Abstract: According to one embodiment, the light guide plate has a first major surface, a second major surface, a side surface, and a recess. The recess is provided in the second major surface. The fluorescent layer is provided in the recess. The light-emitting element is bonded to the fluorescent layer and includes an electrode on a surface of the light-emitting element on a side opposite to a surface of the light-emitting element bonded to the fluorescent layer. The module side surface includes at least a portion of the side surface of the light guide plate. The first interconnect is provided along the second major surface and connected to the electrode of the light-emitting element. The second interconnect is provided on the module side surface and connected to the first interconnect.

Abstract: A semiconductor device of embodiments includes: a semiconductor layer; a first insulating layer provided on the semiconductor layer; a first metal layer provided on the first insulating layer and containing aluminum (Al); a second metal layer provided on the first insulating layer and containing aluminum (Al); and a second insulating layer provided on the first insulating layer, provided between the first metal layer and the second metal layer, having a top surface in contact with a side surface of the first metal layer and a side surface of the second metal layer, and containing silicon (Si) and nitrogen (N).

Abstract: A method for coating chips resting, by a rear face opposite to a front face, on a main face of a support substrate, and separated from each other by an inter-chip space, includes a step of forming a photosensitive coating film covering the front faces and the inter-chip spaces. The method further includes a first photolithographic sequence which comprises an insolation sub-step, and a dissolution sub-step. The sequence leads to a partial removal of the photosensitive coating film so as to maintain the film exclusively at the inter-chip spaces and, advantageously recessed relative to the front faces.

Abstract: A micromechanical component for a pressure sensor device. The component includes a substrate; a frame structure, mounted on a boundary surface of the substrate, including a diaphragm, whose inner diaphragm side borders on an interior volume, framed by the frame structure, so that when a pressure prevailing on its outer diaphragm side is above a reference pressure, the diaphragm is warped into the interior volume; and a rocker structure suspended on the inner diaphragm side, which in its operating mode is set into a rocker motion. An open gap exists between a stop face of the rocker structure and the boundary surface when a pressure prevailing on the outer diaphragm side is above the reference pressure and below a minimum operating pressure. The open gap is closed only when a pressure prevailing on the outer diaphragm side becomes greater or equal to the minimum operating pressure.

Abstract: A package and method of packaging for integrated microfluidic devices and systems is disclosed wherein a package is made from individually processed and patterned layers of LTCC green tape, that is aligned and stacked, and then co-fired to form a stable LTCC ceramic packaging modules. Subsequently, microfluidic device die and/or integrated microfluidic systems device die are bonded to pre-determined areas of the packaging modules and the modules are aligned bonded together to form leak-free, sealed packages for the microfluidic devices and systems. The use of LTCC materials and techniques provides a low-cost flexible and easily customizable packaging approach for microfluidic devices and systems that can be designed and transitioned into production with significant development time and cost.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: An ionic transistor including a first source, a first drain spaced apart from the first source, and a first storage layer electrically connected to the first source and the first drain. The ionic transistor also includes a second source spaced apart from the first source, a second drain spaced apart from the second source, and a second storage layer electrically connected to the second source and the second drain. The ionic transistor further includes an electrolyte layer situated between and electrically connected to the first and second storage layers. The ionic transistor may be implemented as non-volatile memory in a machine learning (ML) application.

Abstract: A first electrode film is electrically connected to a source region of a semiconductor substrate, and disposed over a main surface of the semiconductor substrate. A second electrode film is electrically connected to a gate electrode, and disposed over the main surface. A third electrode film is disposed over the main surface away from the first electrode film. A protective dielectric film is disposed over the main surface, covers only a portion of each of the first electrode film and the second electrode film and covers at least portion of the third electrode film, and is made of a thermosetting resin. The main surface has a peripheral region and an inner region enclosed by the peripheral region, and the protective dielectric film has a peripheral portion covering the peripheral region and has a first inner portion crossing the inner region and covering at least portion of the third electrode film.

Abstract: A micro-electro-mechanical system acoustic sensor, a micro-electro-mechanical system package structure and a method for manufacturing the same are provided. The micro-electro-mechanical system acoustic sensor comprises a substrate, a cantilever structure and a diaphragm sensor. The cantilever structure is formed on the substrate, and comprises a fixed end and a free cantilever portion extended from the fixed end. The free cantilever portion comprises a free end. The free end and the fixed end are respectively at opposing sides of the free cantilever portion. The free cantilever portion is capable of generating a vibration wave in an empty space. The diaphragm sensor is formed on the substrate, and comprises a diaphragm film, a back plate, and at least one electrical contact point. The back plate and the diaphragm film have a first empty gap there between. The empty space and the first empty gap communicate to each other.

Abstract: A production method for a micromechanical component for a sensor or microphone device. The method includes: patterning a plurality of first trenches through a substrate surface of a monocrystalline substrate made of at least one semiconductor material using anisotropic etching, covering the lateral walls of the plurality of first trenches with a passivation layer, while bottom areas of the plurality of first trenches are kept free or are freed of the passivation layer, etching at least one first cavity, into which the plurality of first trenches opens, into the monocrystalline substrate using an isotropic etching method, in which an etching medium of the isotropic etching method is conducted through the plurality of first trenches, and by covering the plurality of first trenches by epitaxially growing a monocrystalline sealing layer on the substrate surface of the monocrystalline substrate made of the at least one identical semiconductor material as the monocrystalline substrate.

Abstract: A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.

Abstract: An acoustic transduction unit, a manufacturing method thereof and an acoustic transducer, and relates to the technical field of electronic devices. A first electrode is arranged on a first substrate, a support layer is arranged on a side, close to the first electrode, of the first substrate, and a conductive diaphragm layer is arranged on a side, away from the first substrate, of the support layer; a cavity is enclosed by the support layer, overlapping areas exist between orthographic projections of the first electrode, the conductive diaphragm layer and the cavity on the first substrate, and the conductive diaphragm layer serves as both a diaphragm layer and a second electrode in the acoustic transduction unit, it allows the conductive diaphragm layer to be configured as both the diaphragm layer and the second electrode, a layer structure of the acoustic transduction unit is simple.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.

Abstract: A micromechanical device that includes a MEMS substrate and a cap substrate that enclose at least one first cavity, with at least one contact pad that is situated outside the first cavity. A MEMS structure is situated in the first cavity and connected to the contact pad with the aid of a strip conductor, the strip conductor extending at least partially in the MEMS substrate. The contact pad is situated at a surface of the cap substrate.

Abstract: An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N? drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET.

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Abstract: Provided is a semiconductor device which includes a semiconductor substrate that has an upper surface and a lower surface. A hydrogen chemical concentration distribution of the semiconductor substrate in a depth direction has a first hydrogen concentration peak and a second hydrogen concentration peak disposed closer to the lower surface side of the semiconductor substrate than the first hydrogen concentration peak. An intermediate donor concentration between the first hydrogen concentration peak and the second hydrogen concentration peak is different from any of an upper surface side donor concentration between the first hydrogen concentration peak and the upper surface of the semiconductor substrate and a lower surface side donor concentration between the second hydrogen concentration peak and the lower surface of the semiconductor substrate. The intermediate donor concentration may be higher than either the upper surface side donor concentration or the lower surface side donor concentration.

Abstract: An active array substrate includes a substrate and a plurality of pixel structure disposed on the substrate. Each of the pixel structure includes a scan line, a data line, and a pixel electrode. The scan line is disposed on the substrate and extending along a first direction. The data line is disposed on the substrate and extending along a second direction. The first direction crosses the second direction. The data line and the scan line define a pixel region and a first cutting clearance region. The pixel electrode is disposed on the substrate and includes a first portion and a second portion. The first portion is on the pixel region. The second portion is on the first cutting clearance region. A normal projection of the second portion onto the substrate does not overlap a normal projection of the data line onto the substrate.

Abstract: An electrical contacting between a surrounding wiring and a conductor region. The conductor region is situated in a conductor layer above an SOI wafer or SOI chip. A cover layer is situated above the conductor layer and below the surrounding wiring. The cover layer has a contacting region. The contacting region is insulated from the rest of the cover layer by a first configuration of recesses. An opening is formed at least in the contacting region. A metallic material is situated in the opening. The metallic material connects the surrounding wiring and the conductor region.