Abstract: The present invention discloses a nonvolatile semiconductor memory device having a memory cell transistor in which an offset region is provided as a charge carrier injecting region. An insulating film and a gate electrode is formed in order of mention on a semiconductor substrate. Source/drain regions are formed on the surface of the semiconductor substrate with the gate electrode interposed therebetween. The drain has an LDD (Lightly Doped Drain) structure. Furthermore, a layered film of silicon oxide films and a SiN film is provided on a channel region between an edge of the gate electrode and a source diffusion layer. To be more specific, the layered film is formed in such a way that the SiN film is interposed between the silicon oxide films, constituting a side wall of the gate electrode. The SiN film is a charge carrier accumulating layer. Contact holes are formed in an insulating film between layers, respectively reaching the source and drain regions.

Abstract: A read only memory (ROM) array is disclosed which includes a) a voltage supply providing an operating voltage level, b) a plurality of word-lines, c) a multiplicity of ROM transistors, and d) a word-line clamper. The ROM transistors are divided into turned on and turned off transistors. Each ROM transistor has a gate connected to one of the word-lines, a gate oxide beneath the gate, whose thickness is less than 250 .ANG., and a channel beneath the gate oxide. The turned off transistors additionally have a ROM implant in their channel whose dosage is no larger than the amount which generates a predetermined desired minimal band-to-band tunneling current The ROM implant and gate oxide thickness define a threshold voltage for the tamed off tranistors, the threshold voltage being less than the operating voltage level. The word-line damper provides a word-line voltage to each of the word-lines, the word-line voltage being clamped to a voltage level no higher than the threshold voltage of the turned off transistor.

Abstract: A semiconductor device with a contact structure includes a silicon substrate, a diffusion region formed in a surface of the silicon substrate, a silicide film of a high melting point metal deposited on the diffusion region, an insulating film formed on the silicon substrate, a contact hole formed in the insulating film such that the silicide film is exposed at a bottom of the contact hole, an anti-diffusion film formed on at least the exposed surface of the silicide film at the bottom of the contact film, a plug formed in the contact hole by selective Al--CVD, and a metal wiring formed on the insulating film. The metal wiring is electrically connected to the diffusion region by the plug, the anti-diffusion film and the silicide film. The anti-diffusion film is formed by nitriding the surface of the silicide film such that only the grain boundaries of the grains of the silicide film are nitrided.

Abstract: Disclosed is a superconducting device comprising a logic SQUID and a readout SQUID magnetically coupled with the logic SQUID, which are fabricated using a single layer of an oxide high-temperature superconductor, wherein the logic SQUID comprising a superconducting loop constituted by a first superconducting line, a second superconducting line arranged to be parallel to the first superconducting line, third and fourth superconducting lines provided to connect the first and second superconducting lines, and two Josephson junctions formed in the third and fourth superconducting lines, and widths W.sub.1 and W.sub.2 of the first and second superconducting lines are larger than a distance d between them, the width W.sub.2 is larger than the width W.sub.1, and the widths W.sub.1 and W.sub.2 are larger than the widths W.sub.3 and W.sub.4 of the third and fourth superconducting lines.

Abstract: A metal foil material for covering a semiconductor device, a semiconductor device covered with the metal foil material, and a process for producing the metal foil-covered semiconductor device are disclosed. The metal foil material is one which is, in molding a resin for encapsulating a semiconductor element using a mold, temporarily fixed on a surface of a cavity of the mold, and is adhered on a surface of a semiconductor device by injecting the encapsulating resin into the mold and molding the resin, wherein a contact angle of the face of the metal foil material which is in contact with the encapsulating resin during molding, to water is 110.degree. or less.

Abstract: An energy relieving, redundant crack stop and the method of producing the same is disclosed. The redundant pattern allows the crack propagating energy that is not absorbed by the first ring of metallization to be absorbed by a second area of metallization and also provides a greater surface area over which the crack producing energy may be spread. The redundant crack stop is produced during the metallization process along with the rest of the wiring of the chip surface and, therefore, no additional production steps are necessary to form the structure.

Abstract: An oriented ferroelectric thin film element, which comprises a single-crystal substrate having thereon (a) a first epitaxial or oriented ferroelectric thin film prepared by a gas phase growth method and (b) a second epitaxial or oriented ferroelectric thin film prepared by application of a coating solution of an organic metal compound to the first ferroelectric thin film followed by heating the coated material. The oriented ferroelectric thin film element has a smooth surface and is useful as an optical guide element, light modulation element, etc. The second ferroelectric thin film can be formed by repeating the process of application of a coating solution of an organic metal compound followed by heating the coated material several times. The present invention also discloses a process for preparing the oriented ferroelectric thin film element.

Abstract: Transition metals (T) of Group VIII (Co, Rh and Ir) have been prepared as semiconductor alloys with Sb, P, and As, having the general formula TX, wherein X is Sb.sub.3, P.sub.3, or As.sub.3. The skutterudite-type crystal lattice structure of these semiconductor alloys and their enhanced semiconductor properties results in semiconductor materials which may be used in the fabrication of power semiconductor devices to substantially improve the efficiency of the resulting semiconductor device. Semiconductor alloys having the desired skutterudite-type crystal lattice structure may be prepared in accordance with the present invention by using vertical gradient freeze techniques, liquid-solid phase sintering techniques, low temperature powder sintering and/or hot-pressing.

Abstract: A bipolar semiconductor comprising layers of SiC semiconductor material. At least one pn-junction is formed between two of the layers having charged carrier transport across the junction when the device is in a conductive state. A resistive element in series with the pn-junction lowers the current through the pn-junction as the voltage drop across the device increases with an increase in temperature. The temperature coefficient for the device switches from a negative to a positive at a lower current through the device.

Abstract: In its gate region (10), a silicon MOS technology component has a surface structure (6) having edges and/or vertices at which inversion regions, suitable as quantum wires or quantum dots, are preferentially formed when a gate voltage is applied. The surface structure is preferably formed as a silicon pyramid (6) by local molecular beam epitaxy.

Abstract: Support for an electrochemical deposit, comprising a substrate (120) and, on the latter, a plurality of first conductive surfaces (128) able to form electrodes, at least one second conductive surface (116) for forming a counterelectrode and means (130, 132, 133, 135) for connecting said first conductive surfaces and said second conductive surface to a voltage source.

Abstract: A field-effect type superconducting device includes a channel layer. The channel layer includes Bi-based oxide compound containing Cu. A source electrode contacts the channel layer. A drain electrode contacts the channel layer. A gate insulating film made of insulating material extends on on the channel layer. A gate electrode extends on the gate insulating film.

Abstract: A material for a semiconductor substrate comprising an aluminum-silicon alloy containing from 50% to 80% by weight of silicon and having a thermal conductivity of 0.28 cal/cm.sec..degree. C. or higher, a coefficient of thermal expansion of 12.times.10.sup.-6 /.degree. C. or smaller and a density of 2.5 g/cm.sup.3 or lower. This material is produced by molding an Al--Si alloy powder, which has been obtained through rapid solidification by atomization, to form a compact and then consolidating the compact by means of forging, sintering, etc. The substrate material may have an Al or Al alloy covering layer at least one surface thereof and, further, as necessary, an insulating or plating layer on the covering layer. The thus obtained substrate material is lightweight and has a suitable coefficient of thermal expansion for a substrate as well as a high thermal conductivity. Therefore, a semiconductor device with high performance and reliability can be obtained using such substrate material.

Abstract: A composite memory material comprising a mixture of active phase-change memory material and inactive dielectric material. The phase-change material includes one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof. A single cell memory element comprising the aforementioned composite memory material, and a pair of spacedly disposed contacts.

Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.

Abstract: A plastic-molded apparatus for a semiconductor laser is disclosed, which comprise: a first lead having a broad end thereof serving as a mounting plate; a second lead located at one side of the first lead; a third lead located at other side of the first lead; a submount, disposed on a front end of the mounting plate, having a semiconductor laser chip disposed thereon, electrically connected to the second lead, and a monitor detector disposed on the mounting plate closely adjacent to the submount, electrically connected to the third lead, for receiving backward light from the semiconductor laser chip; a plastic-molded header to fix the first lead, the second lead and the third lead; and a transparent cap, adapted to the plastic-molded header, for sealing all components including the laser chip, the monitor detector and peripheral parts on the plastic-molded header.

Abstract: A semiconductor functional device includes a semi-insulating semiconductor substrate; a resonant tunneling structure which includes, on the substrate, an n-type collector layer, an epitaxial multilayer structure including a double barrier structure constituted of a plurality of barrier layers holding a well layer therebetween, and an n-type emitter layer; an emitter electrode formed on the emitter layer; and a collector electrode formed on the collector layer. An undoped semiconductor barrier layer is interposed between the semi-insulating semiconductor substrate and the collector layer.

Abstract: The invention provides for a field effect transistor (FET) which includes a substrate and a buffer layer formed upon the substrate and an active layer formed upon the buffer layer. The active layer includes a gate region, drain region and source region. In addition, a channel region is formed in the active layer intermediate the source region and drain region. The channel region includes a first portion of reduced thickness adjacent the drain region. The active layer may include a recess adjacent the drain region to provide the thin channel region. Preferably, the thickness of the first portion of the channel region is equal to the undepleted channel thickness within the second portion of the channel region adjacent the first portion. The substrate, buffer layer, active layer, and degenerate layers are preferably fabricated of silicon carbide or gallium nitride. Further, the FET preferably includes a p type buffer, n type active layer, and n+ degenerate layers.

Abstract: A power MOS chip and package assembly is provided for packaging a power MOS chip that has high heat dissipation. The assembly maintains a low contact resistance to the chip using compression without damaging the chip. The package assembly includes a thermally conductive body, a chip, an electrically conductive contact washer and an external electrical terminal. The chip includes a semiconductor substrate layer, an insulating layer, a conductive material gate layer and a metal layer. The layers form a plurality of first regions that are functionally inactive and a plurality of second regions. The insulating layer is formed to be thicker in the first regions than in the second regions so that the metal layer is elevated with respect to the substrate layer by a greater amount in the first regions than in the second regions. The contact washer is placed in mechanical contact with the chip so that it exerts pressure against the metal layer in the first regions to create an electrical connection.

Abstract: A semiconductor chip package having a clip type lead frame and fabrication thereof. The package includes a semiconductor chip having a plurality of bond pads thereon, a first package body having a recess, a plurality of inner leads each connected electrically to a corresponding one of the bond pads, a plurality of outleads each extended from a corresponding one of the inner leads for covering along sides of the first package body, and a second package body which covers the semiconductor chip, a plurality of metallic wires and the inner leads.