Abstract: A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

Abstract: An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.

Abstract: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract: A thermally enhanced three-dimensional (3D) package is disclosed. The package includes a heat sink having an opening and a stiffener ring inside the opening. The stiffener ring has a first surface and a second surface. A first substrate of a first package is disposed inside the opening and secured to the first surface of the stiffener ring. A second substrate of a second chip package is secured to the second surface of the stiffener ring. The first substrate is connected to the second substrate through a plurality of solder balls. The heat generated in the first chip package and the second chip package is dissipated by the heat sink. The first chip package and the second chip package are fixed by the stiffener ring to eliminate warpage of the first chip package and the second chip package, thereby assuring the electrical transmission of the product.

Abstract: An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and at least one inductance element formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture and the inductance element facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

Abstract: In wafer-level formation of a package structure of semiconductor, multitudes of conductive connection structures are formed protruded from a transparent substrate. Multitudes of grooves are formed in a semiconductor wafer and an adhesive is filled therein. The wafer and the transparent substrate are jointed in which each of the conductive connection structures are positioned in one of the grooves and exposed outside of another surface of the semiconductor wafer. A package structure is obtained by sawing the wafer and has electrical connection between the signals of the active side and back side through the conductive connection structures.