Patents Examined by Scott B. Geyer
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Patent number: 11972906Abstract: A method of producing a capacitor electrode includes forming an oxide layer on a foil. The method also includes inducing defects in the oxide layer followed by reforming the oxide layer. The oxide layer is reformed so as to generate a reformed oxide layer that is an aluminum oxide with a boehmite phase and a pseudo-boehmite phase. The amount of the boehmite phase in the reformed oxide layer is greater than the amount of the pseudo-boehmite phase in the reformed oxide layer.Type: GrantFiled: November 16, 2020Date of Patent: April 30, 2024Assignee: Pacesetter, Inc.Inventors: Ralph Jason Hemphill, James Brian Smith
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Patent number: 11955521Abstract: A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.Type: GrantFiled: October 23, 2020Date of Patent: April 9, 2024Assignee: KYOCERA SLD Laser, Inc.Inventors: James W. Raring, Melvin McLaurin, Alexander Sztein, Po Shan Hsu
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Patent number: 11948980Abstract: A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.Type: GrantFiled: August 29, 2022Date of Patent: April 2, 2024Assignee: KYOCERA SLD Laser, Inc.Inventors: James W. Raring, Melvin McLaurin, Alexander Sztein, Po Shan Hsu
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Patent number: 11942272Abstract: A method for preparing an aramid fiber electrochemical capacitor includes (1) immersing aramid fiber bundles in an aqueous solution; (2) adding polyvinylpyrrolidone into a silver ammonia solution to obtain a solution C, adding an aqueous glucose solution to the solution C to obtain aramid fiber bundles coated with silver nanoparticles; (3) adding the aramid fiber bundles into an aqueous solution containing ?-(2,3-glycidoxy) propyltrimethoxysilane; (4) adding the aramid fiber bundles coated by silver nanoparticles with epoxy groups into an ethanol containing carbon nanotubes with carboxyl groups; (5) adding the aramid fiber bundles with two-layered coatings into an aqueous solution containing pyrrole; (6) heating a mixture of a polyvinyl alcohol, an acid, and water to obtain a polyvinyl alcohol gel, immersing two strands of the aramid fiber bundles, carbon nanotubes and silver nanoparticle in the polyvinyl alcohol gel, and twisting the two strands together to obtain the aramid fiber electrochemical capacitor.Type: GrantFiled: July 4, 2018Date of Patent: March 26, 2024Assignee: SOOCHOW UNIVERSITYInventors: Aijuan Gu, Hao Fang, Guozheng Liang, Li Yuan
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Patent number: 11937516Abstract: Devices, systems, and/or methods that can facilitate local heating of a superconducting flux biasing loop are provided. According to an embodiment, a method can comprise forming on a substrate a biasing loop and a flux controlled qubit device of a superconducting flux bias circuit. The method can further comprise forming a heating device on the substrate to couple the heating device to the biasing loop.Type: GrantFiled: March 4, 2020Date of Patent: March 19, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rasit Onur Topaloglu, Vivekananda P. Adiga, Martin O. Sandberg
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Patent number: 11923396Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.Type: GrantFiled: April 18, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Wei Hsu, Tsai-Hao Hung, Chung-Yu Lin, Ying-Hsun Chen
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Patent number: 11923197Abstract: A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.Type: GrantFiled: April 25, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventor: Gurtej S. Sandhu
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Patent number: 11916054Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.Type: GrantFiled: January 27, 2022Date of Patent: February 27, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Paul M. Enquist, Belgacem Haba
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Patent number: 11901134Abstract: Fabricating a capacitor includes forming conduits in a porous layer of material. The porous layer of material has particles that each includes a dielectric on a core. The formation of the conduits causes a portion of the dielectric to convert from a first phase to a second phase. The method also includes removing at least a portion of the second phase of the dielectric from the porous layer of material.Type: GrantFiled: November 24, 2020Date of Patent: February 13, 2024Assignee: Pacesetter, Inc.Inventors: Ralph Jason Hemphill, David R. Bowen, Thomas F. Strange, Xiaofei Jiang
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Patent number: 11903328Abstract: Devices, methods, and/or computer-implemented methods that can facilitate formation of a self assembled monolayer on a quantum device are provided. According to an embodiment, a device can comprise a qubit formed on a substrate. The device can further comprise a self assembled monolayer formed on the qubit.Type: GrantFiled: February 7, 2020Date of Patent: February 13, 2024Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Richard Alan Haight, Martin O. Sandberg, Vivekananda P. Adiga
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Patent number: 11894199Abstract: A method of manufacturing an aluminum electrolytic capacitor includes impregnating an aluminum electrolytic capacitor with a first electrolyte to form a first impregnated capacitor, aging the first impregnated capacitor using a first aging process to form a first aged capacitor, impregnating the first aged capacitor with a second electrolyte to form a second impregnated capacitor, the second electrolyte being different from the first electrolyte, aging the second impregnated capacitor using a final aging process to form a final aged capacitor, and impregnating the final aged capacitor with a third electrolyte.Type: GrantFiled: June 10, 2021Date of Patent: February 6, 2024Assignee: Pacesetter, Inc.Inventors: Pete J. Fernstrom, Jason Hemphill, Timothy Marshall, Tommy T. Davis, Joseph Beauvais
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Patent number: 11894335Abstract: A method for manufacturing a display device includes preparing a circuit board including a drive circuit for driving a LED chip, forming a connecting electrode on the circuit board, forming an adhesive layer on the connecting electrode, adhering a terminal electrode of the LED chip on the adhesive layer and joining the connecting electrode and the terminal electrode by irradiating a laser light. The adhesive layer may be formed only on a upper surface of the connecting electrode.Type: GrantFiled: June 3, 2021Date of Patent: February 6, 2024Assignee: Japan Display Inc.Inventors: Kazuyuki Yamada, Keisuke Asada, Kenichi Takemasa
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Patent number: 11894412Abstract: A display device includes a substrate having an emission area and a non-emission area, a first electrode and a second electrode spaced from each other on the substrate in the emission area, a first insulating layer on the substrate in the emission area and the non-emission area and covering at least a portion of the first electrode and the second electrode, a light-emitting element between the first electrode and the second electrode, a first contact electrode on the first electrode and in contact with one end portion of the light-emitting element, and a second contact electrode on the second electrode and in contact with the other end portion of the light-emitting element, a first active material layer on the first insulating layer in the non-emission area and electrically connected to the first contact electrode, and a gate insulating layer on the first active material layer.Type: GrantFiled: November 13, 2020Date of Patent: February 6, 2024Assignee: Samsung Display Co., Ltd.Inventors: Sang Ho Park, Sung Hoon Kim, Jin Yeong Kim, Jin Taek Kim, Tae Hoon Yang, Sung Jin Lee
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Patent number: 11887846Abstract: An Atomic Layer Deposition (ALD) method to deposit a metal oxide layer onto an organic photoresist on a substrate using a highly reactive organic metal precursor. The deposition method protects the organic photoresist from loss and degradation from exposure to oxygen species during subsequent ALD cycles. The organic metal precursor may be an amino type precursor or a methoxy type precursor.Type: GrantFiled: February 28, 2020Date of Patent: January 30, 2024Assignee: Lam Research CorporationInventors: Akhil Singhal, Patrick Van Cleemput
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Patent number: 11887861Abstract: A method of processing a substrate, includes: loading the substrate having a silicon-containing film formed thereon into a processing container; a first process of modifying the silicon-containing film by supplying a processing gas containing a halogen-containing gas and a basic gas to the substrate, in a state in which an internal pressure of the processing container is set to a first pressure, to generate a reaction product; a second process of vaporizing the reaction product by setting the internal pressure of the processing container to a second pressure lower than the first pressure; and alternately repeating the modifying the silicon-containing film and the vaporizing the reaction product, wherein subsequent rounds of the first process following the initial first process in the alternately repeating the modifying the silicon-containing film and the vaporizing the reaction product includes supplying the processing gas to the substrate on which the reaction product remains.Type: GrantFiled: January 18, 2021Date of Patent: January 30, 2024Assignee: TOKYO ELECTRON LIMITEDInventor: Jaewon Woo
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Patent number: 11881493Abstract: An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer and first conductive metal layer on the first polysilicon plug; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in the first ILD layer and second conductive metal layer on the second polysilicon plug.Type: GrantFiled: November 21, 2022Date of Patent: January 23, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventor: Ming-Shing Chen
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Patent number: 11875950Abstract: An electrolytic capacitor that includes a resin molded body having opposed first and second end surfaces, the body including a stack that includes a capacitor element with an anode exposed at the first end surface, a dielectric layer on a surface of the anode, and a cathode opposite to the anode and exposed at the second end surface, and a sealing resin that encloses the stack; a first external electrode on the first end surface of the resin molded body and electrically connected to the anode; and a second external electrode on a second end surface of the resin molded body and electrically connected to the cathode, wherein the first external electrode and the second external electrode each include a resin electrode layer containing a conductive component and a resin component.Type: GrantFiled: March 2, 2022Date of Patent: January 16, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yasuhiro Tamatani, Kazuya Kusuda, Kazutoyo Horio, Takeshi Furukawa
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Patent number: 11876026Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.Type: GrantFiled: February 3, 2022Date of Patent: January 16, 2024Assignee: Medtronic, Inc.Inventors: Chunho Kim, Mark E. Henschel
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Patent number: 11869726Abstract: A stacked aluminum electrolytic capacitor includes a lead frame, a capacitor set, and at least one laser welding area. The lead frame includes a positive electrode end and a negative electrode end spaced from the positive electrode end. The capacitor set includes a plurality of stacked capacitor elements each having a positive electrode portion electrically connected to the positive electrode end and a negative electrode portion electrically connected to the negative electrode end. The at least one laser welding area is configured by a laser source capable of emitting a laser beam to perform laser welding on the positive electrode end and the positive electrode portion to form a fusion connection therebetween.Type: GrantFiled: July 19, 2021Date of Patent: January 9, 2024Assignee: Lelon Electronics Corp.Inventors: Shiau Hong Wu, Hui Pin Chen, Chung Ming Wu
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Patent number: 11871682Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); and a second connection part (140) that is provided on a main surface of the interposer (112) where the first connection part (130) is arranged and is connected to a cooling plate (115).Type: GrantFiled: June 16, 2021Date of Patent: January 9, 2024Assignee: NEC CORPORATIONInventors: Kenji Nanba, Ayami Yamaguchi, Akira Miyata, Katsumi Kikuchi, Suguru Watanabe, Takanori Nishi, Hideyuki Satou