Abstract: A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination.

Abstract: The present disclosure relates to an air-cavity package, which includes a substrate, a base, and a semiconductor die. The substrate includes a substrate body, thermal vias extending through the substrate body, and a metal trace on a bottom side of the substrate body and separate from the thermal vias. The base includes a base body, a perimeter wall extending about a perimeter of the base body, and a signal via structure. Herein, the bottom side of the substrate body resides on the perimeter wall to form a cavity, and the signal via structure extends through the perimeter wall and is electrically coupled to the metal trace. The semiconductor die is mounted on the bottom side of the substrate body, exposed to the cavity, and electrically coupled to the metal trace. The thermal vias conduct heat generated from the semiconductor die toward a top side of the substrate body.

Abstract: A substrate processing apparatus includes a rotary table arranged in a vacuum chamber, a first reaction gas supply unit that supplies a first reaction gas to a surface of the rotary table, a second reaction gas supply unit that is arranged apart from the first reaction gas supply unit and supplies a second reaction gas, which reacts with the first reaction gas, to the surface of the rotary table, and an activated gas supply unit that is arranged apart from the first and second reaction gas supply units. The activated gas supply unit includes a discharge unit that supplies an activated fluorine-containing gas to the surface of the rotary table, a pipe that is arranged upstream of the discharge unit and supplies the fluorine-containing gas to the discharge unit, and at least one hydrogen-containing gas supply unit arranged at the pipe for supplying a hydrogen-containing gas into the pipe.

Abstract: A thin film transistor substrate includes a first thin film transistor disposed having a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode and a first drain electrode; a first gate insulating layer between the polycrystalline semiconductor layer and the first gate electrode; a second thin film transistor disposed having an oxide semiconductor layer on the first gate electrode, a second gate electrode on the oxide semiconductor layer, a second source electrode and a second drain electrode; an intermediate insulating layer disposed on the first gate electrode and under the oxide semiconductor layer; and a second gate insulating layer on the intermediate insulating layer and under the first source electrode, the first drain electrode and the second gate electrode.

Abstract: An etching method is provided for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride by performing plasma processing on a target object including the first region and the second region. In the etch method, first, a plasma of a processing gas including a fluorocarbon gas is generated in a processing chamber where the target object is accommodated. Next, the plasma of the processing gas including the fluorocarbon gas is further generated in the processing chamber where the target object is accommodated. Next, the first region is etched by radicals of fluorocarbon contained in a deposit which is formed on the target object by the generation and the further generation of the plasma of the processing gas containing the fluorocarbon gas. A high frequency powers used for the plasma generation is smaller than a high frequency power used for plasma further generation.

Abstract: A method of mounting one or more semiconductor or microelectronic chips, which includes providing a carrier; temporarily adhering the one or more semiconductor or microelectronic chips to the carrier with active faces of the one or more chips facing towards the carrier; providing a package body with at least one chip-receiving opening therein and with at least one contact opening therein; temporarily adhering the package body to the carrier with the at least one opening in the package body accommodating at least a portion of the one or more chips; covering backsides of the one or more chips and filling empty spaces between the one or more chips and walls of the at least one opening in the package body with a metallic material; filling the at least one contact opening with the aforementioned metallic material; wirebonding contacts on the active faces of the one or more chips with contact surfaces in electrical communication with the metallic material in the at least one contact opening; and releasing package b

Abstract: A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.

Abstract: Method embodiments of wafer dicing for backside metallization are provided. One method includes: applying dicing tape to a front side of a semiconductor wafer, wherein the front side of the semiconductor wafer includes active circuitry; cutting a back side of the semiconductor wafer, the back side opposite the front side, wherein the cutting forms a retrograde cavity in a street of the semiconductor wafer, the retrograde cavity has a gap width at the back side of the semiconductor wafer, and the retrograde cavity has sidewalls with negative slope; depositing a metal layer on the back side of the semiconductor wafer, wherein the gap width is large enough to prevent formation of the metal layer over the retrograde cavity; and cutting through the street of the semiconductor wafer subsequent to the depositing the metal layer.

Abstract: A Zener diode includes a semiconductor substrate, an anode electrode and a cathode electrode. The semiconductor substrate includes a p-type anode region, an n-type current path region and a drift region. The p-type anode region is connected to the anode electrode. The n-type current path region is in contact with the anode region. The drift region is in contact with the anode region and the current path region. The drift region is of an n type. The drift region has a lower n-type impurity concentration than the current path region. The drift region is connected to the cathode electrode directly or via another n-type region.

Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.

Abstract: A drift region has a first conductivity type. A well region is at least partially included in an interface area, has an end portion between the interface area and an edge termination area, and has a second conductivity type. An extension region extends outward from the well region, is shallower than the well region, and has the second conductivity type. A plurality of field-limiting rings are provided outside the extension region in the edge termination area. Each of the field-limiting rings together with the drift region located on the inner side forms a unit structure. The field-limiting ring located closer to the outside has a lower proportion of a width to a width of the unit structure. The unit structure located closer to the outside has a lower average dose.

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

Abstract: A semiconductor wafer is provided, where the semiconductor wafer includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. Fins are formed in the semiconductor substrate and the hard mask layer. A spacer is formed on an exposed sidewall of the hard mask layer and the semiconductor substrate. The exposed portion of the semiconductor substrate is etched. A silicon-germanium layer is epitaxially formed on the exposed portions of the semiconductor substrate. An annealed silicon-germanium region is formed by a thermal annealing process within the semiconductor substrate adjacent to the silicon-germanium layer. The silicon-germanium region and the silicon-germanium layer are removed. The hard mask layer and the spacer are removed.

Abstract: A method of producing a contact element for an optoelectronic component includes providing an auxiliary carrier with a sacrificial layer arranged on a top side of the auxiliary carrier; providing a carrier structure having a top side and a rear side situated opposite the top side, wherein an insulation layer is arranged at the rear side of the carrier structure; connecting the sacrificial layer to the insulation layer by an electrically conductive connection layer; creating at least one blind hole extending from the top side of the carrier structure as far as the insulation layer; opening the insulation layer in a region of the at least one blind hole; arranging an electrically conductive material in the at least one blind hole; detaching the auxiliary carrier by separating the sacrificial layer; and patterning the electrically conductive connection layer.

Abstract: A high-frequency conductor having improved conductivity comprises at least one electrically conductive base material. The ratio of the outer and inner surfaces of the base material permeable by a current to the total volume of the base material is increased by a) dividing the base material perpendicularly to the direction of current into at least two segments, which are spaced from each other by an electrically conductive intermediate piece and connected both electrically and mechanically to each other, and/or b) topographical structures in or on the surface of the base material and/or c) inner porosity of at least a portion of the base material compared to a design of the base material in which the respective feature was omitted.