Patents Examined by Seth M. Nehrbass
  • Patent number: 4447824
    Abstract: Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.
    Type: Grant
    Filed: September 10, 1982
    Date of Patent: May 8, 1984
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Logan, John L. Mauer, IV, Laura B. Rothman, Geraldine C. Schwartz, Charles L. Standley
  • Patent number: 4447825
    Abstract: Disclosed is a III-V Group compound semiconductor light-emitting element having a III-V Group compound semiconductor body with a p-n junction and including a p-type layer involved in forming the p-n junction; and a multi-layer electrode mounted on the p-type layer of the semiconductor body. The electrode comprises a first layer of gold alloy containing a small amount of beryllium or zinc and formed in direct contact with the p-type layer of the semiconductor body and an uppermost layer formed of gold or aluminum. A tantalum layer doped with carbon, nitrogen and/or oxygen is formed between the first layer and the uppermost layer by means of vacuum vapor deposition.
    Type: Grant
    Filed: February 2, 1981
    Date of Patent: May 8, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yasuhisa Oana, Nobuaki Yasuda, Masato Yamashita, Norio Ozawa
  • Patent number: 4445134
    Abstract: A highly conductive layer utilizing a layer of Pt in conjunction with sputter deposited or co-evaporated WSi.sub.2 to enhance the conductivity increase of the WSi.sub.2 layer occuring during annealing. The Pt layer is deposited as a thin layer directly on top or beneath the WSi.sub.2 layer or may be incorporated within the WSi.sub.2 layer. During annealing platinum atoms diffuse into the WSi.sub.2 film resulting in lower resistivity values than in comparably deposited annealed film wherein the Pt layer has been omitted.
    Type: Grant
    Filed: November 4, 1981
    Date of Patent: April 24, 1984
    Assignee: IBM Corporation
    Inventor: Robert J. Miller
  • Patent number: 4442450
    Abstract: An improved electronic package having a support substrate, at least one electronic device mounted on the substrate, a cover mounted on the substrate disposed over said device and having a surface in spaced proximity to the device, the improvement being:a thermal bridge for conducting heat from the device to the cover which includes a relatively thick metal sheet provided with cuts that define at least one tab element,grooves in the tab element that make it bendable,and a spring means to selectively urge the tab element into contact with the device.
    Type: Grant
    Filed: March 30, 1981
    Date of Patent: April 10, 1984
    Assignee: International Business Machines Corporation
    Inventors: Lewis D. Lipschutz, Ralph E. Meagher, Frank P. Presti
  • Patent number: 4434434
    Abstract: A controlled geometric configuration of contact pads for securing solder mounds to an integrated circuit chip which reduces cracking of brittle passivating coatings in fabrication of components.
    Type: Grant
    Filed: March 30, 1981
    Date of Patent: February 28, 1984
    Assignee: International Business Machines Corporation
    Inventors: Somnath Bhattacharya, Shih-Ming Hu, Nicholas G. Koopman, Chester C. Oldakowski
  • Patent number: 4408257
    Abstract: A cathode electrode of copper-based material adapted for use in an electrical device is provided with a deposit of silver coated with a finely divided electrically conductive material such as graphite palladium or platinum. The silver deposit is formed by reacting a dilute solution of sodium-silver cyanide with the copper-based cathode electrode. When utilized in an electrolytic capacitor, the cathode electrode helps to increase the capacitance of the cathode electrode and the contact of the copper-based material to an acid electrolyte is uniformly distributed over a large area to provide extended operation with high ripple current with deep cycles of charge and discharge.
    Type: Grant
    Filed: December 8, 1980
    Date of Patent: October 4, 1983
    Assignee: Emhart Industries, Inc.
    Inventor: Charles W. Walters
  • Patent number: 4395747
    Abstract: A low inductance electrolytic capacitor utilizes a stripline on which the capacitor section is wound in extended foil fashion. Each piece of the metal stripline has a projection spaced from one end. The pieces are assembled with an insulating strip between them with the projections at opposite ends and opposite sides of the stripline. The foil extensions are welded directly to the stripline and the stripline to the capacitor terminals.
    Type: Grant
    Filed: April 29, 1981
    Date of Patent: July 26, 1983
    Assignee: Sprague Electric Company
    Inventor: Jack D. White