Abstract: To reduce the influence of generation of after-pulses when a pixel including a SPAD is used. In a SPAD pixel, a PN junction part of a P+ type semiconductor layer and an N+ type semiconductor layer is formed, a P type semiconductor layer having a concentration higher than the concentration of a silicon substrate is formed in a region deeper than the PN junction part and close to a light absorption layer. With no quenching operation generating no after-pulse, electrons generated in the light absorption layer are guided to the PN junction part and subjected to avalanche amplification. When the quenching operation is performed after avalanche amplification, the electrons are guided to the N+ type semiconductor layer by a potential barrier to prevent avalanche amplification. The present disclosure is applicable to an image sensor including a SPAD.

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Abstract: A light-emitting device and a display apparatus including the same are provided. The light-emitting device includes a metal reflective layer having a phase modulation surface, a first electrode on the metal reflective layer, an organic emission layer which is provided on the first electrode and emits white light, and a second electrode on the organic emission layer. The phase modulation surface includes a plurality of protrusions and a plurality of recesses.

Abstract: A display device is provided. The display device includes a substrate including a display area, an opening area disposed in the display area, a first non-display area at least partially surrounding the display area, and a second non-display area at least partially surrounding the opening area. A display layer is disposed in the display area. An encapsulating substrate covers the display layer and has an opening corresponding to the opening area. A sealing portion is disposed between the encapsulating substrate and the substrate. The sealing portion is disposed in the opening area and connects the encapsulating substrate to the substrate. A partition wall is disposed between the substrate and the sealing portion.

Abstract: Provided is a display panel and a method for manufacturing the same, and a display device. The display panel includes a display area and a peripheral area including a first and a second peripheral area. The peripheral area includes a substrate, a first planarization layer and a first dam located above the substrate, the first dam including a corner portion and a straight portion located at the first and second peripheral area respectively. An edge of an orthographic projection of the first planarization layer on the substrate away from the display area is a first edge, an edge of an orthographic projection of the first dam on the substrate close to the display area is a second edge; in the first and second peripheral area, a minimum distance between the first edge and the second edge is a first and a second distance greater than the first distance respectively.

Abstract: A display substrate and a method of manufacturing the same and an electronic device. The display substrate is defined to be an array area and a peripheral area surrounding the array area. The array area includes a plurality of light emitting subunits. Each of the plurality of light emitting subunits includes: a first electrode, a second electrode and a light emitting layer. The first electrodes of the plurality of light emitting subunits are electrically connected with each other. The display substrate further includes a light extraction layer. Projections of the first electrodes of the plurality of light emitting subunits and a projection of the connecting electrode on the base substrate are within a projection of the light extraction layer on the base substrate.

Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.

Abstract: Provided are a method for manufacturing a single-crystal semiconductor layer. The method of manufacturing the single crystalline semiconductor layer includes performing a unit cycle multiple times, wherein the unit cycle includes a metal precursor pressurized dosing operation in which a metal precursor is adsorbed on a surface of a single crystalline substrate by supplying the metal precursor onto the single crystalline substrate while an outlet of a chamber in which the single crystalline substrate is loaded is closed such that a reaction pressure in the chamber is increased; a metal precursor purge operation; a reactive gas supplying operation in which a reactive gas is supplied into the chamber to cause a reaction of the reactive gas with the metal precursor adsorbed on the single crystalline substrate after the metal precursor purge operation; and a reactive gas purge operation.

Abstract: A microsensor for detecting ions in a fluid, comprises: a field-effect transistor having a source, a drain, an active region between the source and the drain, and a gate disposed above the active region, an active layer, in which the active region is formed, a dielectric layer positioned beneath the active layer, a support substrate disposed under the dielectric layer and comprising at least one buried cavity located plumb with the gate of the field-effect transistor in order to receive the fluid.

Abstract: A display apparatus includes a display module including a display surface. The display module includes a display panel including a plurality of display devices which displays an image on the display surface, a plurality of light concentration lenses arranged on the display panel, a buffer layer disposed on the light concentration lenses, and a plurality of diffraction patterns arranged at regular intervals on the buffer layer, where the diffraction patterns diffract a portion of lights incident thereto.

Abstract: The invention relates to a sawing device for forming saw-cuts into a semiconductor product, including: a carrier for holding the semiconductor product, a saw blade, a first position sensor for determining the position of the semiconductor product held by the carrier, a second position sensor for determining the position of the saw blade, and a control unit configured for controlling the relative movement of the saw blade and the carrier, wherein the sawing device further includes a reference for linking the position of the first position sensor to the position of the second position sensor, wherein the control unit is configured to process, with aid of the reference, the positions determined by the reference sensors into a position of the point on the free surface of the semiconductor product relative to the point on the cutting edge of the saw blade, and, based on this positional information, control the relative movement of the saw blade and the carrier.

Abstract: A display device includes a first transistor including a first active layer, a first gate electrode overlapping the first active layer, a gate insulating layer between the first active layer and the first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second active layer, a second gate electrode overlapping the second active layer, a second source electrode and a second drain electrode; a capacitor including a first capacitor electrode connected to the second transistor; a lower electrode disposed under the first active layer; a connecting member connecting the first active layer to the lower electrode; and a first metal pattern contacting the connecting member and disposed on a same layer with the first gate electrode.

Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

Abstract: Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes a plurality of sub-pixels, each sub-pixel of the plurality of sub-pixels defined by adjacent pixel-defining layer (PDL) structures with inorganic overhang structures disposed on the PDL structures, each sub-pixel having an anode, organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material. The device is made by a process including the steps of: depositing the OLED material and the cathode by evaporation deposition, and depositing an encapsulation layer disposed over the cathode.

Abstract: A coating liquid for forming an n-type oxide semiconductor film, the coating liquid including: a Group A element, which is at least one selected from the group consisting of Sc, Y, Ln, B, Al, and Ga; a Group B element, which is at least one of In and Tl; a Group C element, which is at least one selected from the group consisting of Group 4 elements, Group 5 elements, Group 6 elements, Group 7 elements, Group 8 elements, Group 9 elements, Group 10 elements, Group 14 elements, Group 15 elements, and Group 16 elements; and a solvent.

Abstract: Provided are a display substrate and a preparation method thereof, and a display device. The display substrate includes a plurality of pixel units arranged in a matrix, wherein the pixel units each include a plurality of sub-pixels, the sub-pixels each include a micro-cavity modulation layer and an emitting structure layer, the micro-cavity modulation layer is provided with a reflective electrode, the emitting structure layer includes a first electrode, an emitting layer and a semi-transparent and semi-reflective second electrode which are sequentially disposed on the micro-cavity modulation layer, and a distance between the second electrode and the reflective electrode is different in each sub-pixel.

Abstract: Embodiments of the present disclosure include methods of determining scribing offsets in a hybrid laser scribing and plasma dicing process. In an embodiment, the method comprises forming a mask above a semiconductor wafer. In an embodiment, the semiconductor wafer comprises a plurality of dies separated from each other by streets. In an embodiment, the method further comprises patterning the mask and the semiconductor wafer with a laser scribing process. In an embodiment, the patterning provides openings in the streets. In an embodiment, the method further comprises removing the mask, and measuring scribing offsets of the openings relative to the streets.

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

Abstract: A display apparatus is provided. The display apparatus includes a pad spaced away from an encapsulating element. The pad can have a stacked structure of a pad electrode layer and a pad cover layer. A side surface of the pad electrode layer can be covered by the pad cover layer. Thus, in the display apparatus, damage of the pad electrode layer due to a subsequent process can be prevented and as such, the reliability of an external signal transmitted through the pad can be improved.

Abstract: The semiconductor device of the present invention includes a semiconductor layer which includes an active portion and a gate finger portion, an MIS transistor which is formed at the active portion and includes a gate trench as well as a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench at the gate finger portion, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region which is formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.