Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Abstract: A method for determining when to load read I/O operations into an SSD cache medium for a physical storage medium of a data storage system can include maintaining an SSD filter bitmap with a plurality of bits, where each of the bits corresponds to a respective data block of the physical storage medium. The method can also include initially setting each of the bits to a first predetermined value, receiving a first read I/O operation directed to a particular data block of the physical storage medium and, in response to receiving the first read I/O operation, setting a bit corresponding to the particular data block to a second predetermined value. The method can further include receiving a second read I/O operation directed to the particular data block and, in response to receiving the second I/O operation, loading data for the particular data block into the SSD cache medium.

Abstract: Methods for use in a dispersed storage network (DSN) to rebuild data. In various examples, at least one data segment of a data object is dispersed storage error encoded to produce a set of encoded data slices that includes an information dispersal algorithm (IDA) width number of encoded data slices, wherein the IDA width number is at least twice the number of storage units of a set of storage units utilized to store the data object. At least two encoded data slices are stored in each of the storage units. In response to detecting a storage error indicating an error slice, a partial threshold number of partial encoded data slices (generated by performing a partial encoding function on stored encoded data slices) are generated. The partial threshold number of partial encoded data slice responses are combined to produce a rebuilt encoded data slice corresponding to the error slice.

Abstract: Disk-backed array techniques can, in some implementations, help ensure that the arrays contain consistent data. An alert can be provided if it is determined that the data in the array is, or may be, corrupted.

Abstract: Systems and methods for writing data to a storage are disclosed. The disclosed systems and methods can receive, by a target device in communication with a host, a first write request from the host to write first data to the storage in communication with the target device. The disclosed systems and methods can determine, by a storage controller in the target device, a data type of the first data based on a first flag set corresponding to the first data. The disclosed systems and methods can store the first data to a location in the storage based at least on the data type of the first data.

Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.

Abstract: Facilitating processing in a computing environment. A request to access a cache of the computing environment is obtained from a transaction executing on a processor of the computing environment. Based on obtaining the request, a determination is made as to whether a tracking set to be used to track cache accesses is to be updated. The tracking set includes a read set to track read accesses of at least a selected portion of the cache and a write set to track write accesses of at least the selected portion of the cache. The tracking set is assigned to the transaction, and another transaction to access the cache has another tracking set assigned thereto. The tracking set assigned to the transaction is updated based on the determining indicating the tracking set is to be updated.

Abstract: Facilitating processing in a computing environment. A request to access a cache of the computing environment is obtained from a transaction executing on a processor of the computing environment. Based on obtaining the request, a determination is made as to whether a tracking set to be used to track cache accesses is to be updated. The tracking set includes a read set to track read accesses of at least a selected portion of the cache and a write set to track write accesses of at least the selected portion of the cache. The tracking set is assigned to the transaction, and another transaction to access the cache has another tracking set assigned thereto. The tracking set assigned to the transaction is updated based on the determining indicating the tracking set is to be updated.

Abstract: A computer-implemented method according to one embodiment includes identifying a storage volume comprising a plurality of files, calculating a file level input/output operations per second (IOPS) value for each of a subset of the plurality of files within the storage volume, creating a predictive model for the storage volume, using metadata determined for the subset of the plurality of files and the IOPS values calculated for each of the subset of the plurality of files within the storage volume, estimating file level IOPS values for each of the plurality of files in the storage volume, utilizing the predictive model, combining the estimated and calculated file level IOPS values and comparing the combined values to a calculated volume level IOPS value for the storage volume, conditionally adjusting one or more of the estimated file level IOPS values, based on the comparing, and returning the estimated file level IOPS values.

Abstract: Discrete events that take place with respect to a hard disk drive or other I/O device or port are indicated to logic that implements Self-Monitoring Analysis and Reporting Technology (SMART) or similar technology. These events are communicated to SMART as event data. Examples of such discrete events include power on, power off, spindle start, and spindle stop, positioning of the actuator, and the time at which such events occur. SMART then compiles event data to create compiled activity data. Compiled activity data represents summary statistical information that is created by considering some or all of the event data. Examples of compiled activity data include the Time Powered On and Power Cycle Count. Collection logic then writes the compiled activity data to a memory medium. An analyst can then read data from log file(s).

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

Abstract: A computer system includes: a physical resource including a memory; a virtualization mechanism that provides a virtual computer to which the physical resource is allocated; and a cache state management mechanism that manages a cache state of the virtual computer. The virtualization mechanism provides a first virtual computer and a second virtual computer. The cache state management mechanism manages the cache state of each of the first virtual computer and the second virtual computer. When the cache state management mechanism detects transition of the cache state in a state where a memory area allocated to a cache of the first virtual computer and a memory area allocated to a cache of the second virtual computer include duplicated areas storing same data, the virtualization mechanism releases the duplicated area in one of the first virtual computer and the second virtual computer.

Abstract: An information processing apparatus includes a receiver that receives a request for starting backup of data stored in an information processing terminal, from the information processing terminal through a network, and circuitry that allocates a session for backing up data to the information processing terminal based on a number of sessions each performing backup using a file-sharing communication protocol.

Abstract: Provided are a computer program product, system, and method for determining the location for volumes of data being initially stored within a storage space, regardless of the physical location of the data. The storage space includes stripes composed of volumes, which can be logically represented as a utilization histogram of stripe locations offset from one another. Sometime the stripes are fully allocated with one large volume or partially allocated with multiple, arbitrary-sized smaller volumes. When there are multiple smaller volumes that do not utilize all of the available stripe space, gaps form. To minimize the creation of such gaps, when a volume of data is initially stored, a start location to place the volume of data is selected by using selection criteria as guidance.

Abstract: Techniques and mechanisms are provided for migrating data blocks around a cluster during node addition and node deletion. Migration requires no downtime, as a newly added node is immediately operational while the data blocks are being moved. Blockmap files and deduplication dictionaries need not be updated.

Abstract: Embodiments serve to balance overall performance of a finite-sized caching system having a first cache of a first cache size and a second cache of a second cache size. A tail portion and a head portion of each of the caches are defined wherein incoming data elements are initially stored in a respective head portion and wherein evicted data elements are evicted from a respective tail portion. Performance metrics are defined wherein a performance metric includes a predicted miss cost that would be incurred when replacing an evicted data elements. A quantitative function is defined to include cache performance metrics and a cache reallocation amount. The cache performance metrics are evaluated periodically to determine a then-current cache reallocation amount. The caches can be balanced by increasing the first cache size by the cache reallocation amount and decreasing the second cache size by the cache reallocation amount.

Abstract: An arithmetic processing device includes a plurality of core units, each including a plurality of cores each having a arithmetic and logic unit, and a cache memory shared by the plurality of cores; a home agent connected to the cache memories provided respectively in the core units; and a memory access controller connected to the home agent and controls access to a main memory. The cache memories each includes a data memory having cache blocks, and a first tag which stores a first state indicating a MESI state, for each of the cache blocks, and the home agent includes a second tag which stores a second state including at least a shared modify state in which dirty data is shared by cache memories, for each of the cache blocks in the cache memories provided respectively in each of the core units.

Abstract: Identifying data for placement in a storage system having a plurality of storage classes includes subdividing the data into portions, for each of the portions, independently determining at least one score for a particular portion based on a metric corresponding to access of the particular portion, where the at least one score for the particular portion is independent of scores for other ones of the portions, and identifying sub-portions of data for placement in a particular storage class based on the at least one score of a portion of data corresponding to the sub-portions. The at least one score may be based on short term access statistics and long term access statistics. The access statistics may include read misses, writes, and prefetches.

Abstract: A memory device includes a first storage unit storing an address mapping table, and a control unit coupled to the first storage unit and including a second storage unit storing a risky mapping table and a cached mapping table. The control unit is configured to: write data into the first storage unit; update mapping information associated with the data in the risky mapping table; and store mapping information in the cached mapping table into the address mapping table.

Abstract: A method for maintaining an index in multi-tier data structure includes providing a plurality of a storage devices forming the multi-tier data structure, caching an index of key-value pairs across the multi-tier data structure, wherein each of the key-value pairs includes a key, and one of a data value and a data pointer, the key-value pairs stored in the multi-tier data structure, providing a journal for interfacing with the multi-tier data structure, providing a plurality of zone allocators recording which zones of the multi-tier data structure are in used, and providing a plurality of zone managers for controlling access to cache lines of the multi-tier data structure through the journal and zone allocators, wherein each zone manager maintains a header object pointing to data to be stored in an allocated zone.