Patents Examined by Shih-Wei Kraft
  • Patent number: 9772867
    Abstract: Embodiments relate to a control area for managing multiple threads in a computer. An aspect is a computer system that includes a virtual machine (VM) configuration with one or more cores. Each core is enabled to operate in a single thread (ST) mode or a multithreading (MT) mode. The ST mode consists of a single thread and the MT mode consists of a plurality of threads on shared resources of a respective core. The computer system includes a core-oriented system control area (COSCA) having a common area representing all of the cores of the VM configuration and separate core description areas for each of the cores in the VM configuration. Each core description area indicates a location of one or more thread description areas each representing a thread within the respective core, and each thread description area indicates a location of a state description of the respective thread.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
  • Patent number: 9654515
    Abstract: Service Capability Interaction Manager (SCIM)-type functionality is provided at a horizontal service layer in an Service Oriented Architecture (SOA)-based approach. SCIM composition is provided at multiple levels, including the level of composition where servlets have full access to the context information of the service layer. SCIM composition also occurs at the level of an application dispatching messages to multiple applications/services for processing the messages. The functionality at the service layer also can be programmed using policies, such that routing decisions can be made dynamically as the result of processing conditions and actions. An incoming message can result in a Web service being triggered that in turn triggers a BPEL or SOA workflow, the workflow calling multiple operations to process the message as a result of a routing table or header, environmental and contextual information at the service level, and other information such as user preference or presence information.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: May 16, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Stephane H. Maes
  • Patent number: 9645863
    Abstract: In an image forming device which is capable of executing an application program, a plurality of interface providing units are arranged each providing the application program with an interface which enables the application program to use a function of the image forming device. A selecting unit selects at least one of the plurality of interface providing units as an object of use for the application program based on a result of comparison of information stored in a storage device and indicating an execution environment of each of the plurality of interface providing units with information stored in the storage device and indicating an execution environment of the image forming device.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: May 9, 2017
    Assignee: RICOH COMPANY, LTD.
    Inventor: Kunihiro Akiyoshi
  • Patent number: 9645867
    Abstract: A computer implemented method provides shuffle optimization in map-reduce processing. The computer implemented method obtains intermediate results from a plurality of mappers for an application on a computing device. The intermediate results are combined from the plurality of mappers and are then partitioned into intermediate results for respective reducers for the application. The intermediate results for the respective reducers are stored into a buffer storage, which is partitioned into buffer sections for the respective reducers. Based on a rate of increase in the intermediate results, the method predicts a time at which a data capture notification shall be sent. The method sends the data capture notification based on a predicted time being reached, to indicate that the intermediate results for respective reducers stored in the buffer storage can be transmitted to the respective reducers, and transmits the intermediate results for the respective reducers to the respective reducers.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Liang Liu, Junmei Qu, Chao Qiang Zhu, Wei Zhuang
  • Patent number: 9639453
    Abstract: Techniques are disclosed for automatically determining tests to run on source code based on code coverage. In one embodiment, an extensible system takes as input a configuration file having pointers to an IP address of a server where tests are being run and a type of code coverage instrumentation. An agent configured to instrument source code and collect code coverage information is copied to the server at the IP address. During a training phase, the agent intercepts tests being run on source code and provides a dump of the interception results after each test is executed. Using such results, mappings of the tests to the source code is created and stored. During an execution phase, when new or modified source code file is being checked in, a testing application retrieves for execution tests which map to the source code file and to code dependent on the source code file.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: May 2, 2017
    Assignee: VMware, Inc.
    Inventor: Rekha Belur
  • Patent number: 9633321
    Abstract: A method for facilitating electronic commerce over a network includes identifying input dependencies for a call request based on information passed with the call request, identifying state dependencies for the call request based on information passed with the call request, parallelizing calls from the call request based on at least one of the identified input dependencies and the identified state dependencies, developing a service execution map by grouping calls in an execution order including parallelized calls, and processing the service execution map by executing grouped calls in the execution order including parallelized calls.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: April 25, 2017
    Assignee: PAYPAL, INC.
    Inventors: Mohammed Saleem Shafi, Elmustafa E. Erwa
  • Patent number: 9626232
    Abstract: Queue storage queues event entries from a hardware event detector that are to be communicated to a software event handler. An event register stores a most recently received event entry. A comparator compares a newly received event entry with the content of the event register and if a match occurs, then these event entries are merged by setting a merged entry bit and discarding the newly received event entry. When a non-matching event entry is received, then the unqueued event within the event register is stored into the queue storage. If the queue storage is empty, then the event register and the comparator are bypassed. When the queue storage becomes empty, then any currently unqueued event within the event register is stored into the queue storage. The event entries may be translation error event entries in a system which translates between virtual addresses and physical addresses.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: April 18, 2017
    Assignee: ARM Limited
    Inventor: Fabrice Jean Verplanken
  • Patent number: 9621634
    Abstract: A processor records statistics regarding invocation of a second component of a distributed computing system by a first component of the distributed computing system. The processor determines a dependency between the first component and the second component based on the statistics and determines a dependency rating for the dependency based on the statistics. The processor migrates the first component from a first location to a second different location. Responsive to determining that the dependency rating for the dependency exceeds a dependency threshold, the processor migrates the second component to the second location.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: April 11, 2017
    Assignee: Red Hat, Inc.
    Inventor: Mark Cameron Little
  • Patent number: 9612872
    Abstract: A method for allocating data plane resources. The method allocates segments of hardware data plane resources to individual domains. In particular, in one or more embodiments, a new domain data plane request may request multiple segments of hardware data plane resources. In response to the request, a segment is reserved for a domain by assigning a domain identifier of the domain to the segment. Thus, the domain may use the allocated segment.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 4, 2017
    Assignee: Ciena Corporation
    Inventor: Jaffar Hameed Abdul Kather Jilani
  • Patent number: 9563468
    Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes identifying a memory location and sending a probe request from the first processor to the additional processors. The probe request includes the memory location. The computer implemented method further includes generating, by each additional processor, an indication including whether the memory location is in use for a transaction by the additional processor. The computer-implemented method further includes sending the indication from each additional processor to the first processor and proceeding, by the first processor, based on the indication.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9563490
    Abstract: For systems integration, an information published about an application programming interface (API) of a service is parsed to extract a pattern from the information. the pattern is compared with a stored pattern in a repository, wherein the stored pattern corresponds to a known API. When the pattern matches the stored pattern within a threshold degree of match, a conclusion is made that the API of the service is the known API. A collector code module is selected where the collector code module is configured to call the known API. The collector code module is sequenced in an integration sequence, to call the known API. A forwarder code module is also sequence din the integration sequence to forward a data output of the service to a consumer application.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark D. Batinich, Linwood E. Loving, Luigi Pichetti
  • Patent number: 9563467
    Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes identifying a memory location and sending a probe request from the first processor to the additional processors. The probe request includes the memory location. The computer implemented method further includes generating, by each additional processor, an indication including whether the memory location is in use for a transaction by the additional processor. The computer-implemented method further includes sending the indication from each additional processor to the first processor and proceeding, by the first processor, based on the indication.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9558049
    Abstract: Shuffle optimization in map-reduce processing. The method includes: obtaining intermediate results from a plurality of mappers for an application on a computing device; combining the intermediate results from the plurality of mappers; and partitioning the combined intermediate results into intermediate results for respective reducers for the application based on respective keys of the combined intermediate results.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Liang Liu, Junmei Qu, Chao Qiang Zhu, Wei Zhuang
  • Patent number: 9542448
    Abstract: The technology relates to techniques for the attachment of priorities and/or reaction time limits to various entities of a system such as, for example, events, event types, queries, etc. The system's processing may be tailored behavior to match these boundary conditions while at the same time increasing (and sometimes even maximizing) the rate of events processed. Advantageously, the system may be made to adapt its behavior to the current situation, which is changeable and may even be changing quite frequently, e.g., as in connection with a potentially rapidly changing stream. Users may, for example, specify policies to control this adaptation and, thus, events (including events of special interest) may be handled appropriately, even in response to changing conditions.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: January 10, 2017
    Assignee: SOFTWARE AG
    Inventor: Harald Schöning
  • Patent number: 9535608
    Abstract: A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Michael Karl Gschwind, Valentina Salapura, Timothy J. Slegel
  • Patent number: 9514048
    Abstract: In a transactional memory environment, a computer-implemented method includes a first processor initiating a first transaction and encountering an abort condition. Responsive to the abort condition, an abort other request is communicated between the first processor and one or more additional processors. The one or more additional processors receive the abort other request, and, responsive to the abort other request, the one or more additional processors selectively abort a current second transaction based on the abort other request and an abort other condition. Optionally, the transactional memory environment supports a transaction category scheme, whereby each transaction has associated therewith a category identifier. In such embodiments, the abort other request includes an abort category identifier, and the abort other condition includes aborting the current second transaction if the abort category identifier matches the category identifier for the current second transaction.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Valentina Salapura, Chung-Lung K. Shum
  • Patent number: 9513960
    Abstract: In a transactional memory environment, a computer-implemented method includes a first processor initiating a first transaction and encountering an abort condition. Responsive to the abort condition, an abort other request is communicated between the first processor and one or more additional processors. The one or more additional processors receive the abort other request, and, responsive to the abort other request, the one or more additional processors selectively abort a current second transaction based on the abort other request and an abort other condition. Optionally, the transactional memory environment supports a transaction category scheme, whereby each transaction has associated therewith a category identifier. In such embodiments, the abort other request includes an abort category identifier, and the abort other condition includes aborting the current second transaction if the abort category identifier matches the category identifier for the current second transaction.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Valentina Salapura, Chung-Lung K. Shum
  • Patent number: 9507628
    Abstract: A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: November 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Michael Karl Gschwind, Valentina Salapura, Timothy J. Slegel
  • Patent number: 9507652
    Abstract: Two threads may communicate via shared memory using two different modes. In a polling mode, a receiving thread may poll an indicator set by the sending thread to determine if a message is present. In a blocking mode, the receiving thread may wait until a synchronization object is set by the sending thread which may cause the receiving thread to return to the polling mode. The polling mode may have low latency buy may use processor activity of the receiving thread to repetitively check the indictor. The blocking mode may have a higher latency but may allow the receiving thread to enter a sleep mode or perform other activities.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: November 29, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Erez Haba
  • Patent number: 9483290
    Abstract: Methods and systems for a virtual environment are provided. A method includes receiving a packet from a first virtual machine at a virtual switch; determining if the packet is destined to a second virtual machine by comparing a destination address to a mapping data structure maintained by the virtual switch; transferring the packet to a first virtual function of a device assigned to the first virtual machine by directly mapping the first virtual function to the first virtual machine; the first virtual function initiating a direct memory access (DMA) operation to transfer the packet to the second virtual machine based on a logical memory address of the second virtual machine that is received from a second virtual function; and using the DMA operation to transfer the packet to the second virtual machine.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: November 1, 2016
    Assignee: QLOGIC, Corporation
    Inventors: Neeraj Mantri, Tanmay Pradip Shete