Patents Examined by Shrinivaj H Rao
  • Patent number: 6300197
    Abstract: In a method of manufacturing a semiconductor device having MIS field effect transistors (MIS-FETs) with gate insulating films of two or more different film thicknesses formed on the same silicon semiconductor substrate, first, impurity for enhancing the growth rate of a gate insulating film is selectively doped into an element region on which the gate insulating film is to be formed thick and which is contained in element regions in which the MIS-FETs are to be formed. On the other hand, impurity for lowering the growth rate of a gate insulating film is selectively doped into an element region on which the gate insulating film is to be formed thin and which is contained in the element regions in which the MIS-FETs are to be formed. Next, gate insulating films are formed on the respective element regions by use of the anodic oxidation method or the like.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: October 9, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Inaba