Abstract: A novel high-speed, highly reliable VSLI manufacturable metal oxide semiconductor transistor with self-aligned punchthrough stops. A gate insulating layer is formed on a substrate having a first concentration of a first conductivity type. An inner gate electrode of a predetermined length and width is formed on the gate insulating layer. The inner gate electrode has laterally opposite sidewalls along the width of the inner gate electrode. A first and second punchthrough stop regions of a second concentration of the first conductivity type wherein the second concentration is greater than the first concentration, are disposed in the substrate in alignment with the laterally opposite sidewalls of the inner gate electrode. A pair of conductive spacers adjacent to and in electrical contact with respective laterally opposite sidewalls of the inner gate electrode are formed on the gate insulating layer of the transistor. The conductive spacers, along with the inner gate electrode, form a MOSFET gate electrode.

Abstract: A method of manufacturing a semiconductor device utilizing a multi-chamber apparatus comprises the steps of forming a metal film on an insulating layer under the lower pressure within a film forming apparatus and reflowing the metal film on the insulating film, after transferring the semiconductor substrate to a reflow apparatus from the film forming apparatus under the vacuum atmosphere of 1.3×10−6 Pa or less, by simultaneously heating a plurality of semiconductor substrates under the vacuum atmosphere of 1.3×10−6 Pa or less.

Abstract: A novel method of forming a polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notched nitride layer over the tip. At the same time, a method of forming a self-aligned source (SAS) line is disclosed. A relatively thin polygate is formed so as to decrease the growth of the protrusion of conventional gate bird's beak (GBB) to a smaller and sharper tip. It will be known by those skilled in the art that GBB is easily damaged during conventional poly etching where polyoxide is used as a hard mask. To use polyoxide as a hard mask, thick polysilicon is needed in the first place. Such thick poly will increase gate coupling ratio, which has the attendant effect of degrading program and erasing performance of the memory cell.

Abstract: A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (“EMOD”) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO2, CeO2, Y2O3 or (Ce1-xZrx)O2, wherein 0≦x≦1.

Abstract: A transistor and a method for making a transistor are described. A silicon gate conductor is patterned over a gate dielectric upon a silicon substrate. Dopant impurity distributions self-aligned to the gate conductor may be introduced. Silicon nitride (“nitride”) spacers are formed adjacent to opposed sidewall surfaces of the gate conductor. Oxide caps are formed covering exposed outer surfaces of the nitride spacers. The oxide caps prevent dissociation of the nitride spacers during a subsequent pre-amorphization implant. A preclean is subsequently used to remove oxides from the surfaces of the gate conductor and semiconductor substrate. The preclean may also remove the oxide caps, but does not attack the nitride spacers. A salicide process is used to form low-resistance gate, source, and drain silicides.