Abstract: A data accessing method using data protection with aid of an Advanced Encryption Standard (AES) processing circuit, and associated apparatus such as memory device, memory controller, and the AES processing circuit are provided. The data accessing method includes: utilizing the memory controller to start receiving first protected data corresponding to a read request from predetermined storage space; utilizing the AES processing circuit to start performing decryption processing on the first protected data to obtain decrypted data; utilizing the AES processing circuit to start performing encryption processing on other data to obtain encrypted data to be second protected data corresponding to a write request; and utilizing the memory controller to start sending the second protected data to the predetermined storage space, for storing the second protected data into the predetermined storage space. The AES processing circuit can perform encryption and decryption simultaneously.

Abstract: Embodiments of the present disclosure relate to method and apparatus for scaling out storage devices, and scaled-out storage devices by establishing a cross-device link between a first storage device and a second storage device; exchanging configuration information of at least one of the first storage device and the second storage via the cross-device link; creating, in the first storage device, a shadow object corresponding to a real object in the second storage device; and creating, in the second storage device, a shadow object corresponding to a real object in the first storage device; wherein each shadow object can expose feature and/or state of a corresponding real object to users without implementing a functioning logic of the corresponding real object.

Abstract: A dataflow graph for an application has operation units that are configured to be producers and consumers of tensors. A write access pattern of a particular producer specifies an order in which the particular producer generates elements of a tensor, and a read access pattern of a corresponding consumer specifies an order in which the corresponding consumer processes the elements of the tensor. The technology disclosed detects conflicts between the producers and the corresponding consumers that have mismatches between the write access patterns and the read access patterns. A conflict occurs when the order in which the particular producer generates the elements of the tensor is different from the order in which the corresponding consumer processes the elements of the tensor. The technology disclosed resolves the conflicts by inserting buffers between the producers and the corresponding consumers.

Abstract: Systems and methods for metadata compaction in a distributed storage system with a file system interface are described. A file system interface and an object storage system interface use a metadata index for mapping object identifiers from the object storage system to location identifiers for the file system. When the metadata index includes a number of entries for continuous data blocks with overlapping intervals, a defragmentation operation may generate a defragmented entry for a defragmentation interval overlapping the overlapping data blocks.

Abstract: A memory system includes a memory device, and a memory controller including a processor and an internal memory. A computer program including a neural network is stored in the memory system. The processor executes the computer program to extract a voltage level from each of a plurality of memory cells connected to one string select line (SSL), in which the memory cells and the SSL are included in a memory block of the memory device, provide the voltage levels as input to the neural network, and perform noise cancellation on the SSL, using the neural network, by changing at least one of the voltage levels from a first voltage level to a second voltage level. The first voltage level is classified into a first cluster of memory cells, and the second voltage level is classified into a second cluster of memory cells different from the first cluster.

Abstract: A data caching circuit and method are provided. The circuit is configured to cache data for a feature map calculated by a neural network, wherein a size of a convolution kernel of the neural network is K*K data, and a window corresponding to the convolution kernel slides at a step of S in the feature map, where K is a positive integer and S is a positive integer, the circuit comprising: a cache comprising K caching units, each caching unit being configured to respectively store a plurality of rows of the feature map, the plurality of rows comprising a corresponding row in every K consecutive rows of the feature map.

Abstract: A mechanism is provided by which a hardware accelerator detects migration of a software process among processors and uses this information to write operation results to an appropriate cache memory for faster access by the current processor. This mechanism is provided, in part, by incorporation within the hardware accelerator of a mapping table having entries including a cache memory identifier associated with a processor identifier. The hardware accelerator further includes circuitry configured to receive a processor identifier from a calling processor, and to perform a look-up in the mapping table to determine the cache memory identifier associated with the processor identifier. The hardware accelerator uses the associated cache memory identifier to write results of called operations to the cache memory associated with the calling processor, thereby accelerating subsequent operations by the calling processor that rely upon the hardware accelerator results.

Abstract: Methods, systems, and devices for a memory access gate are described. A memory device may include a controller, memory dice, and a pad for receiving an externally provided control signal, such as a chip enable signal. The memory device may include a switching component for selecting the externally provided control signal or an internally generated control signal. The controller may provide the selected control signal to a memory die. The memory device may determine whether it is operating in a first mode or a second mode, and select the externally provided control signal or the internally generated control signal based on the determination. The first mode may be a diagnostic mode in some cases. The controller may include a secure register whose value may impact or control the switching. An authenticated host device may direct the controller to write the value to the secure register.

Abstract: An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.

Abstract: Methods and devices for hardware-supported schemes for efficient metadata retrieval are described. The schemes may use hardware to efficiently enforce type safety and speed up memory bound checks without imposing undue memory overhead. Multiple such schemes may be supported by a device, permitting the selection of an optimal scheme based on a given memory allocation request. The schemes may be compatible with legacy code and applicable to a wide range of data objects and system constraints. Compilation, instrumentation, and linking of code to effect such schemes is also described.

Abstract: An information handling system includes a memory subsystem; a processor; and a link connecting the processor and memory subsystem, the processor having a memory controller to manage load instructions; a data cache to hold data for use by the processor; a load store unit to execute load instructions; an instruction fetch unit to fetch load instructions and a cache line utility tracker (CUT) table having a plurality of entries, each entry having a utility field to indicate the portions of a cache line of the load instruction that were used by the processor. The system configured to: determine whether the load instruction is in the CUT Table and in response determine from the CUT Table whether to request a partial cache line; and in response to the data not being in the data cache, transmit a memory request for a partial cache line.

Abstract: An indication of a maximum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks is received from a host application, wherein no maximum retention time is indicated for a second plurality of tracks. In response to demoting a track of the first plurality of tracks from the first type of memory to the second type of memory, an adjustment of a first amount of time that the track is allowed to be retained in the second type of memory is based on a second amount of time the track has already been present in the first type of memory prior to being demoted from the first type of memory to the second type of memory.

Abstract: An example system may comprise a network-attached storage device including a base station having a hardware interface including a drive port and a connectivity port; a modular storage drive attachable to and detachable from the drive port; and a modular wireless adapter attachable to and detachable from the connectivity port. The portable storage device is formable by detaching the modular storage drive and the modular wireless adapter from the hardware interface of the network-attached storage device, and coupling the modular storage drive and the modular wireless adapter to one another via a portable hardware interface. Further, a rechargeable modular power unit is removable from the base station and attachable to and detachable from a power port of the network-attached storage device.

Abstract: Provided are techniques for using a memory subsystem for a workload job. A section of a memory subsystem is allocated to a workload job, where the memory subsystem is comprised of a plurality of heterogeneous memory devices. In response to a track being modified for the workload job in a cache, it is determined that modified tracks have reached a threshold portion of the cache. In response to determining that the track exists in the section of the memory subsystem, data in the track in the section of the memory subsystem is overwritten with data in the track in the cache. in response to determining that the track does not exist in the section of the memory subsystem, the data in the track in the cache is copied to the track in the section of the memory subsystem, and the track is demoted from the cache.

Abstract: A method, computer program product, and computing system for receiving a request to reconfigure a data array that currently includes N data drives and P parity drives to include N data drives and P+1 parity drives; confirming the availability of the P+1 parity drive; and distributing a plurality of new parity portions across the N data drives and P+1 parity drives.

Abstract: A new snapshot of a storage volume is created by instructing computing nodes to suppress write requests. An orchestration layer implements a multi-role application that is provisioned with virtualized storage and computation resources. A snapshot of the application may be created and used to rollback or clone the application. Clones snapshots of storage volumes may be thin clones. An application may use multiple orchestration approaches and objects of the multi-role application may be discovered and added to an application definition. The application definition may be used to create snapshots of the application and perform operations using the snapshots. Rolling back may include deleting objects other than PVCs, followed by rolling back storage volumes mounted to the PVCs, followed by recreating objects according to an application snapshot. PVCs created by a custom resource may be deleted along with the custom resource with the PVCs being recreated before recreating the custom resource.

Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

Abstract: A system and method for accessing redundancy array of independent disks (RAID) are provided. The system is coupled between a central processing unit (CPU), a main memory and the RAID, and includes an arithmetic circuit, a register and a disk controller. The arithmetic circuit is coupled to the CPU and the main memory, and is configured to access data from the main memory. The arithmetic circuit calculates a plurality of syndromes of the data to be written and store the calculated syndromes of the plurality of syndromes into the main memory. The register is coupled to the arithmetic circuit, and is configured to store a calculation progress of the plurality of syndromes need to be calculated by the arithmetic circuit. The disk controller is coupled to the register and the RAID, and is configured to read the calculation progress from the register, and according to the calculation progress, to store the calculated syndromes of the plurality of syndromes from the main memory to the RAID.

Abstract: A method, system, and computer readable storage medium for managing computer memory by an intelligent memory manager. The intelligent memory manager performs a method including: initializing a memory allocator within an intelligent memory manager in a computing system; allocating, by the memory allocator, a plurality of main memory objects; backing up, with the intelligent memory manager, at least one main memory object in the plurality of main memory objects in a persistent storage utilizing a backup operation; monitoring, with the intelligent memory manager, input-output bandwidth being consumed for storing information in the persistent storage; and modifying, with the intelligent memory manager, the backup operation based on monitoring the bandwidth being consumed.

Abstract: A higher-level system that inputs and outputs data to/from a storage area including one or more logical areas respectively provided from one or more NVM drives manages the storage area, and manages a plurality of chunks that are a plurality of areas forming the storage area, each of the chunks being a unit of data input/output and being an non-overwritable area. Each of the plurality of chunks has the same chunk size, and each of the plurality of chunks includes a part of each of one or more logical areas. Each of the plurality of chunks includes, for each of the one or more NVM drives, all or part of one or more logical blocks that are one or more ranges corresponding to one or more physical blocks, respectively, but does not include at least a part of a logical block that is entirely or partially included in another chunk.