Abstract: Phase locked loop (PLL) detection circuit that can improve the stability of operation, avoid occurrence of an erroneous operation, and perform PLL lock judgment correctly. Whether a PLL circuit that consists of a phase comparator, a low-pass filter, and a VCO is in a lock state is judged based on a phase error signal in the PLL circuit. The level of the phase error signal is compared with two threshold values, VRL and VRH. When the phase error signal is somewhere between VRL and VRH, a judgment is made that the PLL circuit is in a lock state. A judgment that the PLL circuit is out of a lock state is made in the other cases. This makes it possible to output a correct and stable PLL lock judgment signal.

Abstract: A phase-locked loop bandwidth is tuned to a desired level by operating the phase-locked loop in a phase-locked condition at a first frequency and applying a step response to the phase-locked loop by causing the phase-locked loop to begin locking to a second frequency that is different from the first frequency. A parameter is then detected that is related to the applied step response and that is indicative of whether the phase-locked loop bandwidth is at the desired level. The phase-locked loop bandwidth is adjusted, and the steps of operating at the first frequency, applying the step response, detecting the parameter and adjusting the phase-locked loop bandwidth are repeated until the phase-locked loop bandwidth is at the desired level. Where the desired bandwidth level for tuning is not the operational bandwidth, the phase-locked loop bandwidth is further adjusted by a predetermined amount, thereby tuning the phase-locked loop bandwidth to an operational level.

Abstract: A digitally temperature compensated oscillator (TCO) system is provided which is capable of memorizing in an EEPROM-based look-up table, appropriate digital values of a temperature correction for a voltage controlled oscillator (VCO). An on-board temperature sensing mechanism tracks variations in temperature in the TCO and produces an analog voltage value corresponding to the instantaneous temperature. The voltage value of the sensor output is digitized and designated to constitute an address into the EEPROM based look-up table. As the temperature changes, the digitized output of the temperature sensor and hence the address to the EEPROM changes accordingly. The EEPROM also includes a look-up table of digitized channel tuning voltage values for tuning the VCO to at least one frequency for transmitting or receiving at least one channel, for example in the FRS group of channels. One of these digitized values is selected in response to operator selection of a channel.

Abstract: A demodulating system for estimating frequency offset and sampling time error by a Fast Fourier Transform operation, which receives a modulated signal sent from a GMSK (Gaussian Low-Pass Filtered Minimum Shift Keying) or a MSK (Minimum Shift Keying) transmitter and demodulates the signal. The demodulating system uses a Fast Fourier Transform converter to obtain frequency offset and sampling time error by applying to it an initial demodulated result generated from a discriminator or a phase differentiator.

Abstract: A Gaussian Minimum Shift Keying modulator that provides direct modulation of a carrier signal, produced by a single microwave high power voltage controlled oscillator. A continuous phase frequency shift keyed modulated signal with a modulation index of 0.5 is produced at the desired output frequency using a full 360 degree linear continuous phase modulator, controlled by a linear baseband signal that is the integral of the binary baseband information signal. This modulated signal is used as the reference signal for a phase locked high power voltage controlled oscillator. The phase locked loop provides frequency tracking and Gaussian spectral shaping to the modulated output signal.

Abstract: A method and an apparatus for forming a pulse amplitude modulated signal in association with digital modulation. In the method symbols to be transmitted are formed from bits of an incoming bit stream. In order to achieve an accurate timing even when a bit clock contains abundant jitter, sample values of a pre-low-pass-filtered waveform of a pulse to be transmitted, covering at least one symbol period, are stored in a memory, sample values are read from the memory at the rate of a constant-frequency clock signal (f.sub.c, 4.times.f.sub.c), and a sample value read from the memory is multiplied by a predetermined factor the value of which is formed as a response to the symbol being transmitted.

Abstract: In a phase locked loop (PLL) (308), an edge proximity detector (302) identifies a phase error, indicative of a difference between a phase of a reference frequency signal (115) and a phase of an output frequency signal (116 or 117), as either desirable or undesirable. When the phase error is identified as desirable, a counter (301) determines a rate of change of the phase error over a first predetermined time period (412) to provide an indication of frequency error (306) between the frequency of the reference frequency signal (206) and the frequency of the output frequency signal (116 or 117); and a loop bandwidth adjuster (310) controls a transition between a first and a second loop bandwidth state of the PLL (308) responsive to the indication of the frequency error (306). When the phase error is identified as undesirable, the PLL (308) operates in the second loop bandwidth state. The present invention advantageously provides an accurate determination of when to vary the loop bandwidth of the PLL (308).

Abstract: An accurate RC oscillator circuit (10) for generating a signal of a predetermined frequency that accurately oscillates between two precise voltage levels, i.e., a low threshold voltage (V.sub.L) and a high threshold voltage (V.sub.H). The oscillator circuit uses first and second comparators (16, 18) having their outputs respectively coupled to set and reset inputs of a flip flop (20). The output of the flip flop is coupled to a series RC network for controlling the charging and discharging of the voltage across a capacitor (14) of the RC network. The interconnection (12) of the series RC network is coupled to an input of both the first and second comparators. The other input of the first comparator is coupled to a circuit (24) for applying a modified version (V'.sub.H) of the high threshold voltage such that the signal generated by the oscillator circuit does not exceed the precise high threshold voltage (V.sub.H).

Abstract: A differential delay stage for a ring oscillator utilizes a resonant circuit formed by an inductor and a capacitor consisting of two varactor diodes connected back-to-back. A common cathode connection is connected to a variable voltage source to vary the capacitance of the diodes. Other forms of capacitors may replace the varactor diodes. Varying the capacitance value varies the resulting oscillation frequency of the ring oscillator. When several delay stages, each incorporating the resonant circuit, are connected together in a ring, the net effect is to allow only a signal at the resonant frequency of the resonant circuits to propagate around the ring. Other oscillator circuits employing a resonant circuit are disclosed.

Abstract: An oscillator comprises a comparator and first and second switches for alternately connecting first and second respective reference voltages to a first input of the comparator. A capacitor is connected to a second input of the comparator, and a current source and a current sink are alternately connected to the capacitor via third and fourth switches. The first and third switches are closed simultaneously based on one output level of the comparator, and the second and fourth switches are closed simultaneously based on the other output level of the comparator. This causes the output of the compartor to alternate and thereby generate an oscillation signal. To provide precision in the duty cycles, either the second reference voltage, the current source or the current sink is adjusted to maintain desired duty cycles of the high and low levels output from the comparator.

Abstract: This invention is a three layer Si.sub.x Ge.sub.1-x structure formed on a silicon substrate in which a thin, lightly doped Si.sub.x Ge.sub.1-x layer is formed between two heavily doped Si.sub.x Ge.sub.1-x layers. The incorporation of at least 10% germanium in the silicon provides for intervalley scattering of carriers in the conduction band of the Si.sub.x Ge.sub.1-x layers. This intervalley scattering leads to the negative differential conductance necessary for transferred electron device (TED) operation. Additionally, the lightly doped Si.sub.x Ge.sub.1-x layer is made very thin, on the order of 2,000 to 7,000 Angstroms, and the current flow through the this layer is vertical so that a high electric field can be placed across the lightly doped layer without applying a high voltage across the lightly doped layer. The lightly doped layer can be made thin even though it is interposed between two heavily doped layers because the growth of the in-situ doped Si.sub.x Ge.sub.

Abstract: A frequency locked loop frequency synthesizer is comprised of a loop including a voltage controlled oscillator, a phase lock locked loop frequency detector, a divide by N counter and a low pass loop filter. A steering voltage is applied to the loop filter to produce a desired frequency or frequencies. The frequency lock loop frequency synthesizer drives the voltage controlled oscillator frequency to be N times the reference frequency. The frequency lock loop synthesizer inherently has 90 degrees less loop phase shift than a conventional phase lock loop. Additionally, the frequency lock loop frequency synthesizer provides a highly accurate, continuously tuneable, frequency synthesizer that includes a linear frequency detector in the frequency lock loop.

Abstract: A Costas loop carrier recovery device with particular application to communications with spacecraft includes a voltage-controlled oscillator. Two filters having different characteristics are connected to the oscillator by a loop filter via two circuits:a direct connection, anda parallel circuit including an amplifier in series with a filter.

Abstract: An ultra low noise oscillator circuit including a crystal and having two outputs. At the two outputs, the signal is correlated and the noise outside of the crystal bandwidth is decorrelated. Summing the two outputs in a hybrid circuit significantly reduces oscillator phase noise by almost 3 dB. In addition, these outputs can be used to perform a single oscillator noise test on the oscillator or crystal.

Abstract: In a direct digital synthesizer providing a frequency modulated output the modulation input is bit shifted and the rate of the direct digital synthesizer phase accumulation is controlled to provide enhanced FM deviation resolution.

Abstract: In a demodulating circuit, for example, for demodulating an amplitude- or frequency-modulated signal, analog-to-digital converted values are obtained at a plurality of sampling points in each cycle of the modulated signal, such converted values are integrated to provide a calculated integration value for the respective cycle, and the calculated integration value is compared with a maximal integration value derived in the same manner so as to obtain the demodulated output.

Abstract: A negative-resistance diode oscillator tuned by a varactor as applicable to frequency-modulated transmitters or to receiver oscillators operating within the 56-100 GHz frequency band is integrated in a waveguide. The diode is encapsulated in a capped package and mounted on a ground-connected base. A coupling capacitor is fixed on the metallic cap of the package. A varactor having beam-lead connections is mounted as a bridge between the capacitor and a ground-connected metallic stud. The bias voltages are brought in the plane of the waveguide by means of two wires and two capacitors housed within orifices formed through the waveguide walls.

Abstract: A sidelock avoidance scheme for preventing sidelock in a PSK demodulator's carrier recovery loop contains augmenting sweep control circuitry, including a frequency discriminator and an associated window comparator. The output of the frequency discriminator, which is low pass filtered to remove noise, is applied to the window comparator which compares any differential between the true carrier and the output of a carrier recovery loop to a preset reference threshold representative of a frequency error condition that may approach sidelock. When the output of the frequency discriminator is greater that this preset reference threshold, an augmented frequency control voltage is applied to the voltage control oscillator of the loop to drive the oscillator away from a possible sidelock condition and toward the true carrier. The augmented frequency control voltage may be derived from a frequency sweep generator or from the output of the frequency discriminator, depending upon a selected strapping option.

Abstract: A tuning assembly is disclosed for selectively oscillating the frequency of an electromagnetic field within a hermetically sealed device, which device includes a rigid, hermetically sealed housing, apparatus for generating the electromagnetic field therewithin, and elements for defining a cavity within the housing for establishing the frequency of the electromagnetic field. The tuning assembly includes electrically conductive members mounted for linear movement within the cavity to selectively vary the volume of the cavity to oscillate the established frequency. Elements disposed within the rigid housing are provided for mounting the electrically conductive members, and are adapted for oscillatory movement at a pre-determined mechanical resonant frequency to move the electrically conductive members in the described linear manner. Finally, a power source is provided exterior to the rigid housing and is magnetically coupled to the mounting elements for exciting the mounting elements.