Patents Examined by Sitaramarao S Yechuri
-
Patent number: 11978812Abstract: A waveguide photodetector includes a first contact layer of a first conductivity type, a waveguide layer, and a second contact layer of a second conductivity type that are sequentially formed on the semiconductor substrate. The waveguide layer includes a first cladding layer of the first conductivity type disposed on a side of the first contact layer, a second cladding layer of the second conductivity type disposed on a side of the second contact layer, and the core layer disposed between the first cladding layer and the second cladding layer. The core layer includes a light absorption layer and an impurity-doped light absorption layer that has a higher concentration of a p-type impurity than that of the light absorption layer and is disposed on a side of a light incident face.Type: GrantFiled: February 26, 2020Date of Patent: May 7, 2024Assignee: Mitsubishi Electric CorporationInventor: Ryota Takemura
-
Patent number: 11973159Abstract: Provided is a photodetector which can be manufactured in a standard process of a mass-produced CMOS foundry. The photodetector includes a silicon (Si) substrate; a lower clad layer; a core layer including a waveguide layer configured to guide signal light, and including a first Si slab doped with first conductive impurity ions and a second Si slab doped with second conductive impurity ions; a germanium (Ge) layer configured to absorb light and including a Ge region doped with the first conductive impurity ions; an upper clad layer; and electrodes respectively connected to the first and second Si slabs and the Ge region. A region of the core layer sandwiched between the first Si slab and the second Si slab operates as an amplification layer.Type: GrantFiled: August 28, 2019Date of Patent: April 30, 2024Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Kotaro Takeda, Kiyofumi Kikuchi, Yoshiho Maeda, Tatsuro Hiraki
-
Patent number: 11961935Abstract: A detection base plate and a flat-panel detector. The detection base plate comprises multiple detection pixel units arranged in an array. Each detection pixel unit comprises: a thin-film transistor, a sacrificial layer and a photoelectric conversion part that are disposed on a substrate, wherein the sacrificial layer is located between the thin-film transistor and the photoelectric conversion part; the thin-film transistor comprises an active layer, a first electrode and a second electrode; at least part of an orthographic projection of the active layer on the substrate is located within an orthographic projection of the sacrificial layer on the substrate; and the photoelectric conversion part is electrically connected to the sacrificial layer and the first electrode. In the detection base plate, the sacrificial layers of the detection pixel units are mutually independent.Type: GrantFiled: June 22, 2021Date of Patent: April 16, 2024Assignees: BEIJING BOE SENSOR TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Jianxing Shang, Xiangmi Zhan, Zhenwu Jiang, Huinan Xia, Xuecheng Hou
-
Patent number: 11963457Abstract: A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.Type: GrantFiled: December 12, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng, Vinh Lam, Yi Yang
-
Patent number: 11961941Abstract: An LED array comprises a first mesa comprising a top surface, at least a first LED including a first p-type layer, a first n-type layer and a first color active region and a tunnel junction on the first LED, a second n-type layer on the tunnel junction, the second n-type layer comprising at least one n-type III-nitride layer with >10% Al mole fraction and at least one n-type III-nitride layer with <10% Al mole fraction. The LED array further comprises an adjacent mesa comprising a top surface, the first LED, a second LED including the second n-type layer, a second p-type layer and a second color active region. A first trench separates the first mesa and the adjacent mesa, cathode metallization in the first trench and in electrical contact with the first and the second color active regions of the adjacent mesa, and anode metallization contacts on the n-type layer of the first mesa and on the anode layer of the adjacent mesa.Type: GrantFiled: March 3, 2023Date of Patent: April 16, 2024Assignee: Lumileds LLCInventors: Robert Armitage, Isaac Wildeson
-
Patent number: 11954275Abstract: A display panel and a display device are provided. By providing a winding structure with a hollow part on an electrode trace of a touch function layer, a parasitic capacitance between the touch function layer and a cathode layer at a pillar can be reduced. Furthermore, an overall consistency of the parasitic capacitance between the touch function layer and the cathode layer is balanced, noise caused by imbalance of the parasitic capacitance is avoided, and an overall touch report rate and sensitivity are improved.Type: GrantFiled: August 21, 2020Date of Patent: April 9, 2024Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Jian Ye
-
Patent number: 11955395Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.Type: GrantFiled: June 30, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
-
Patent number: 11949034Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodetector and methods of manufacture. The structure includes: a photodetector; and a semiconductor material on the photodetector, the semiconductor material comprising a first dopant type, a second dopant type and intrinsic semiconductor material separating the first dopant type from the second dopant type.Type: GrantFiled: June 24, 2022Date of Patent: April 2, 2024Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: John J. Ellis-Monaghan, Rajendran Krishnasamy, Siva P. Adusumilli, Ramsey Hazbun
-
Patent number: 11940271Abstract: A method of preparing a computer processor die includes determining a warpage shape of the computer processor die at a testing temperature. The method also includes selectively contouring a thickness of the computer processor die at a contouring temperature by physically removing material from a surface of the computer processor die such that the surface will be substantially flat at the testing temperature.Type: GrantFiled: November 17, 2020Date of Patent: March 26, 2024Assignee: International Business Machines CorporationInventors: David J. Lewison, Jay A. Bunt, Frank L. Pompeo, Richard Walter Oldrey, John D. Sylvestri, Phong T. Tran
-
Patent number: 11935989Abstract: An optoelectronic semiconductor chip may include a first region doped with a first dopant, a second region doped with a second dopant, an active region between the first and second regions, a first contact layer having an electrically conductive material and covering the first region. An insulating layer may cover the first contact layer and include first openings, and the insulating layer may include a second contact layer having an electrically conductive material and covering the insulating layer and the first openings. The first openings may completely penetrate the insulating layer, and the second contact layer may include second openings and/or a third contact layer comprising an electrically conductive material is arranged in the first openings in each case between the second contact layer and the insulating layer.Type: GrantFiled: May 15, 2020Date of Patent: March 19, 2024Assignee: OSRAM Opto Semiconductors GmbHInventors: Fabian Kopp, Attila Molnar, Roland Heinrich Enzmann
-
Patent number: 11937449Abstract: A sealing structure (200) seals a light emitting unit (140) and includes a first inorganic film (210), a second inorganic film (220), a first resin-containing film (230), and a second resin-containing film (240). The film thickness of the first inorganic film (210) is equal to or greater than 1 nm and equal to or less than 300 nm. The first resin-containing film (230) is in contact with the first inorganic film (210) and includes a first resin. The second inorganic film (220) is positioned on an opposite side of the first inorganic film (210) with the first resin-containing film (230) interposed between the first and second inorganic films. The second resin-containing film (240) is positioned between the first resin-containing film (230) and the second inorganic film (220) and is in contact with the second inorganic film (220). The second resin-containing film (240) includes a second resin.Type: GrantFiled: December 2, 2022Date of Patent: March 19, 2024Assignee: PIONEER CORPORATIONInventor: Shinichi Tanisako
-
Patent number: 11937453Abstract: The present disclosure relates to a display device, a display panel, and a method for manufacturing the display panel. The display panel includes a substrate, a display layer and a light-shielding layer. The display layer includes a driving circuit layer and an insulating planarization layer covering the driving circuit layer which are stacked sequentially on the substrate, the display layer is provided with at least one through hole penetrating through the display layer, and the insulating planarization layer has a side wall close to the at least one through hole. The light-shielding layer covers at least partial region of the side wall of the insulating planarization layer.Type: GrantFiled: June 29, 2020Date of Patent: March 19, 2024Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Pinfan Wang
-
Patent number: 11935956Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.Type: GrantFiled: June 26, 2020Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Kevin P. O'Brien, Carl Naylor, Chelsey Dorow, Kirby Maxey, Tanay Gosavi, Ashish Verma Penumatcha, Shriram Shivaraman, Chia-Ching Lin, Sudarat Lee, Uygar E. Avci
-
Patent number: 11923253Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.Type: GrantFiled: February 10, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuei-Ming Chang, Rei-Jay Hsieh, Cheng-Han Wu, Chie-luan Lin
-
Patent number: 11923471Abstract: An avalanche diode including a gain region and a readout structure including an n-type (p-type) region having electrically isolated segments each including implanted regions; a p-type (n-type) region; and a first electrode on each of the segments. The gain region includes a p-n junction buried between the n-type region and the p-type region: an n+-type region having a higher n-type dopant density than the n-type region; a p+-type region having a higher p-type dopant density than the p-type region; and the p-n junction between the n+-type region and the p+-type region. A bias between the first electrodes and a second electrode (ohmically contacting the p-type (n-type) region) reverse biases the p-n junction. Electrons generated in response to electromagnetic radiation or charged particles generate additional electrons m the gain region through impact ionization but the segmented region comprises a low field region isolating the gain region from the first electrodes.Type: GrantFiled: October 30, 2020Date of Patent: March 5, 2024Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Carolyn Gee, Simone Michele Mazza, Bruce A. Schumm, Yuzhan Zhao
-
Patent number: 11923467Abstract: A semiconductor device for infrared detection comprises a stack of a first semiconductor layer, a second semiconductor layer and an optical coupling layer. The first semiconductor layer has a first type of conductivity and the second semiconductor layer has a second type of conductivity. The optical coupling layer comprises an optical coupler and at least a first lateral absorber region. The optical coupler is configured to deflect incident light towards the first lateral absorber region. The first lateral absorber region comprises an absorber material with a bandgap Eg in the infrared, IR.Type: GrantFiled: June 4, 2020Date of Patent: March 5, 2024Assignee: AMS AGInventors: Gerald Meinhardt, Ingrid Jonak-Auer, Gernot Fasching, Bernhard Löffler
-
Patent number: 11915980Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.Type: GrantFiled: December 12, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ya-Yi Tsai, Yi-Hsuan Hsiao, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
-
Patent number: 11901465Abstract: The optical sensor includes a substrate, a first transistor for functioning as a light-receiving element and a second transistor for writing/reading in a pixel region provided on the substrate. The first transistor is formed by a transistor using polycrystalline silicon, the second transistor is formed by a transistor using an oxide semiconductor. A light-shielding layer is provided on the back side of the oxide semiconductor of the second transistor. Thus, it is possible to irradiate light to the optical sensor fora long time, and in addition to increasing the amount of light received by the first transistor, it is possible to suppress variations in the characteristics of the second transistor.Type: GrantFiled: June 16, 2022Date of Patent: February 13, 2024Assignee: Japan Display Inc.Inventor: Masashi Tsubuku
-
Patent number: 11901385Abstract: A semiconductor package includes a semiconductor chip structure that includes an image sensor chip and a logic chip that contact each other, a transparent substrate disposed on the semiconductor chip structure, and an adhesive structure disposed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate. The adhesive structure includes a first adhesive segment disposed on a top surface of the semiconductor chip structure and a second adhesive segment disposed on a bottom surface of the transparent substrate. The second adhesive segment covers top and lateral surfaces of the first adhesive segment. The image sensor chip is closer to the transparent substrate than the logic chip.Type: GrantFiled: June 17, 2021Date of Patent: February 13, 2024Assignee: SAMSUNG ELECTRONICS CO, LTD.Inventor: Byoungrim Seo
-
Patent number: 11901378Abstract: A problem to be solved is to prevent deterioration of a signal-to-noise ratio. A photodetector according to the present invention is a germanium photodetector (Ge PD) that uses germanium or a germanium compound in a light absorption layer, the photodetector including a resistor connected in series with a cathode or an anode of the Ge PD; and a capacitor connected at one end to a connection point between the resistor and a cathode or anode of the Ge PD and grounded at another end, another connection point of the resistor being connected to a bias power supply, wherein to withstand maximum operating optical input power, the value of the resistor is determined such that electric power applied to the Ge PD will be lower than a breakdown threshold.Type: GrantFiled: January 14, 2020Date of Patent: February 13, 2024Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventor: Kotaro Takeda