Abstract: A memory device and associated techniques for programming a select gate transistor. The programming of the select gate transistors in a NAND string is performed under similar biasing as is seen during the programming of a memory cell, when the select gate transistors are required to be in the conductive or non-conductive state for selected and unselected NAND strings, respectively. Program-verify tests for the select gate transistors use a current which flows from the source end to the drain end of the NAND string, and can be performed separately for odd- and even-numbered NAND strings, to avoid the effects of bit line-to-bit line coupling. The tests account for uneven doping in the channel of the select gate transistor. Program-verify tests for the memory cells use a current which flows from the drain end to the source end and can be performed concurrently.

Abstract: A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for incrementing the number of program and erase cycles when the erase-suspend limit has been reached.

Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.

Abstract: A memory device includes a memory array including a plurality of memory cells that store data, a sense circuit coupled to the memory array for reading data stored in the memory array, a data register for storing data to be written into the memory array, a data processor, and a control unit. The data processor is configured to receive input data units to be written into the memory array, and process the input data units based on array data units stored in the memory array to generate processed data units. The control unit is configured to write the processed data units into the memory array.

Abstract: A memory device includes a memory cell array including a plurality of memory cells; a counting circuit configured to obtain a counting result by performing a counting operation on data read from the plurality of memory cells; and a control logic configured to perform a data restoring operation based on the counting result without involvement of a memory controller.

Abstract: A method for operating a memory system including a memory controller and a memory module, the method includes: by the memory controller, applying a read command to the memory module; by the memory module, determining whether the memory module is able to transfer the read data to the memory controller during a regulated section; by the memory module, notifying the memory controller by using a data strobe signal that the memory module is not able to transfer the read data to the memory controller during the regulated section; by the memory controller, applying a status check-out command to the memory module in response to the notification for checking out a status of the memory module; and by the memory module, transferring status information of the memory module to the memory controller in response to the status check-out command.

Abstract: A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target profile including distribution targets, wherein each of the distribution targets represent a program-verify target corresponding to a logic value for the memory cells, determine a feedback measure based on implementing a processing level for processing data, and dynamically generate an updated target based on adjusting the program-verify target according to the feedback measure.

Abstract: Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.

Abstract: A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.

Abstract: A semiconductor memory device includes first and second memory cells, first and second word lines that are connected to the first and second memory cells, respectively, a first transistor connected to one end of the first word line, and second and third transistors respectively connected to first and second ends of the second word line. During a read operation on the first and second memory cells, when the first word line is selected, a first voltage is applied to the second word line, and then a second voltage is applied to the first word line, and when the second word line is selected, the first voltage is applied to the first word line, and then the second voltage is applied to the second word line. The second voltage is applied to the first word line for a longer duration than is applied to the second word line.

Abstract: Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.

Abstract: A sequence of storage devices of a data store may include one or more stripesets for storing data stripes of different lengths and of different types. Each data stripe may be stored in a prefix or other portion of a stripeset. Each data stripe may be identified by an array of addresses that identify each page of the data stripe on each included storage device. When a first storage device of a stripeset becomes full, the stripeset may be shifted by removing the full storage device from the stripeset, and adding a next storage device of the data store to the stripeset.

Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.

Abstract: An electronic device includes a semiconductor memory, and the semiconductor memory includes a memory cell including a resistive memory element having a high resistance state and a low resistance state according to stored data, a selection element coupled serially to the resistive memory element, and a current clamping transistor electrically connected to a first end of the memory cell to limit an amount of a current flowing through the memory cell. In a drift recovery operation of the memory cell, a rising pulse voltage may be applied to a second end of the memory cell in a state in which the current clamping transistor has been turned off, the first end facing the second end.

Abstract: A data storage apparatus includes a nonvolatile memory device and a controller configured to determine whether or not one or more addresses of defective bit lines are included in an address of a write data to be written into the nonvolatile memory device or an address of a read data read from the nonvolatile memory device, and write the write data or read the read data by skipping the defective bit lines based on a determination result.

Abstract: A power supply circuit and a semiconductor storage device that can achieve low power consumption of the power supply circuit that includes a charge pump circuit are provided. The semiconductor storage device includes a charge pump unit which generates and outputs a boosted voltage by boosting a source voltage, a voltage monitoring unit that performs comparison and determination on magnitudes of a divided voltage obtained by dividing the boosted voltage and a predetermined reference voltage, a charge pump control unit that causes the charge pump unit to operate when the divided voltage is equal to or lower than the reference voltage and causes the charge pump unit to stop when the divided voltage is higher than the reference voltage based on a result of the comparison and determination, and a voltage monitoring control unit that causes the voltage monitoring unit to intermittently stop.

Abstract: A battery pack in one aspect of the present disclosure includes a rechargeable battery, a rewritable nonvolatile memory, a write request receiver, and a write controller. The rewritable nonvolatile memory includes storage areas including a write-inhibit area. The write request receiver receives a write request and data from a charger. The write request includes a first address assigned to a first storage area of the storage areas. The data includes a first data element. The write controller executes a write process for the received data. The write process includes avoiding writing the first data element to the first storage area in response to determining that the first storage area is the write-inhibit area.

Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.

Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.