Abstract: A semiconductor device is provided where it is possible to access and test a memory chip by a simple method. The semiconductor device that mounts a plurality of chips in a common package includes a logic chip having a predetermined function and a memory chip that is coupled with the logic chip and stores data. The memory chip includes a memory chip testing circuit that performs an operation test of the memory chip and a serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and a serial bus provided outside the package.

Abstract: The invention is notably directed to a resistive memory device comprising a control unit for controlling the resistive memory device and a plurality of memory cells. The plurality of memory cells includes a first terminal, a second terminal and a phase change segment comprising a phase-change material for storing information in a plurality of resistance states. The phase change segment is arranged between the first terminal and the second terminal. The phase change material consists of antimony. Furthermore, at least one of the dimensions of the phase change segment is smaller than 15 nanometers. Additional implementations of the resistive memory device include a related method, a related control unit, a related memory cell and a related computer program product.

Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.

Abstract: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

Abstract: A semiconductor memory device includes a memory cell array, a temperature sensor that generates a first voltage which is based on a temperature of the semiconductor memory device, compares the first voltage with a second voltage that is based on a result of previous temperature measurement, and generates a voltage generation signal based on a result of comparing the first voltage with the second voltage, and a voltage generating circuit that generates a voltage applied to the memory cell array based on the voltage generation signal.

Abstract: An anti-fuse device includes a program transistor and a read transistor. The program transistor executes a program via insulation breakdown of a gate insulating layer. The read transistor is adjacent to the program transistor and reads the state of the program transistor. At least one of a first gate electrode of the program transistor or a second gate electrode of the read transistor is buried in a substrate.

Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.

Abstract: Disclosed is a hand-held control (1) for furniture drives (81), comprising a touch-sensitive control panel section (3, 3a, 3b) that has a number of actuation surfaces (4). A method for detecting actuation of the hand-held control (1) is also provided. An electromotive furniture drive (81) is fitted with a hand-held control (1) of this type.

Abstract: A multiple instruction, multiple data memory device includes a memory array with several sections, one or more multiplexers between the sections and a decoder. Each section has memory cells arranged in rows and columns. The cells in a row are connected by a read enabled word line and by a write enabled word line. The decoder includes a decoder memory array which generally simultaneously activates a plurality of read enabled word lines in several sections, a plurality of write enabled word lines in several sections and one or more multiplexers. The decoder memory array includes several bit lines oriented perpendicularly to and connected to the rows of the memory array. A method of activating in-memory computation using several bit lines of a decoder memory array, connected to rows of the memory array to simultaneously activate several read enabled word lines, several write enabled word lines and one or more multiplexers.

Abstract: A semiconductor apparatus includes a sense amplifier configured to sense data transmitted through a data line and a sense amplifier control circuit configured to detect whether a level of an external voltage is equal to or larger than an reference voltage level and control a power voltage of the sense amplifier according to a detection result.

Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Abstract: A level shifter includes an input control unit suitable for outputting an output control signal according to a pulse width of a data signal and a pulse width of an input control signal; and an output control unit suitable for controlling an output driving signal according to the output control signal.

Abstract: A self-tracked bistable latch cell includes a cross-coupled latch, and two programmable transistors. The cross-coupled latch has a first data terminal, a second data terminal, a first voltage input terminal for receiving a latch control signal, and a second voltage input terminal for receiving a reference voltage. The first programmable transistor has a first terminal for outputting a first bit, a second terminal coupled to the first data terminal of the cross-coupled latch, and a control terminal for receiving a track control signal. The second programmable transistor has a first terminal for outputting a second bit, a second terminal coupled to the second data terminal of the cross-coupled latch, and a control terminal for receiving the track control signal. The gate oxide of both the first and the second programmable transistor are thinner than the gate oxide of the transistor of the cross-coupled latch.

Abstract: According to one embodiment, a memory device includes a controller, and a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks, the erase operation executing every block, the nonvolatile memory transferring a first reply showing a completion of the erase operation and a fail bit count showing a number of memory cells in which a data erase is uncompleted after the completion of the erase operation to the controller. The controller selects a target block as a target of the erase operation based on the fail bit count.

Abstract: The present disclosure relates to a structure which includes a dual write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line of the memory cell array.

Abstract: A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.

Abstract: A controller adapts read voltage thresholds of a non-volatile memory. In one embodiment, in response to selection of a block for adaptation of at least one read voltage threshold applicable to a physical page of the block, the controller issues a dummy read operation to the block to ensure the physical page is in a lower bit error rate (BER) state. The controller waits for a calibration read wait period following the dummy configuration read operation and, during the calibration read wait period, monitors for an interfering access to the non-volatile memory that would temporarily place the physical page in a higher BER state. In response to not detecting the interfering access during the calibration read wait period, the controller performs a calibration read operation for the physical page and adapts at least one read voltage threshold for the physical page based on results of the calibration read operation.

Abstract: A memory device includes: a cell array connected to a plurality of word lines and bit lines, the cell array including a plurality of memory cells each including a variable resistance element and a bidirectional selection element; a selection circuit that selects a selected word line and a selected bit line; and control logic that controls the selection circuit such that in a stand-by state, wherein the word lines and the bit lines which are connected to memory cells of a first area of the cell array are maintained in a discharge state, and the word lines and bit lines which are connected to memory cells of a second area of the cell array are maintained in a precharge state.