Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: An OLED display panel and a display device are provided. A photoresist structure of a color filter layer is a stack of two defining layers, a sloped surface is defined between corresponding defining areas of two defining layers, and a color resist unit of the color filter layer is formed in corresponding color resist defining areas and corresponds to a light-emitting unit, which reduces a usage of color filter materials and prevents solvent volatilizing to the environment by using solvent-free color filter materials.

Abstract: There is provided a method of manufacturing a semiconductor device, including forming a metal nitride film substantially not containing a silicon atom on a substrate by sequentially repeating: (a) supplying a metal-containing gas and a reducing gas, which contains silicon and hydrogen and does not contain a halogen, to the substrate in a process chamber by setting an internal pressure of the process chamber to a value which falls within a range of 130 Pa to less than 3,990 Pa during at least the supply of the reducing gas, wherein (a) includes a timing of simultaneously supplying the metal-containing gas and the reducing gas; (b) removing the metal-containing gas and the reducing gas that remain in the process chamber; (c) supplying a nitrogen-containing gas to the substrate; and (d) removing the nitrogen-containing gas remaining in the process chamber.

Abstract: A flexible display panel is provided, which includes a base substrate, a thin film transistor (TFT) array layer, and an encapsulation layer. The TFT array layer includes an inorganic layer. An organic layer is disposed on the TFT array layer in a non-display region. The organic layer is defined with a hollow structure at least penetrating the organic layer and the encapsulation layer covers the hollow structure. The organic layer includes a planarization layer, a pixel definition layer, and a support layer. The hollow structure includes grooves with different groove levels, which improves a bending resistance of the flexible display panel and prevents cracks from extending to a display region.

Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

Abstract: A method of manufacturing a semiconductor device includes forming a dummy gate structure on a substrate, partially removing the dummy gate structure to form a first opening that divides the dummy gate structure, forming a first division pattern structure in the first opening, replacing the dummy gate structure with a gate structure, removing the first division pattern structure to form a second opening, removing a portion of the gate structure from a sidewall of the second opening to enlarge the second opening, and forming a second division pattern in the enlarged second opening.

Abstract: A semiconductor structure includes a gate structure surrounding a plurality of channels and a cut feature that electrically isolates two separate portions of the gate structure. The cut feature comprises an outer layer having a work-function metal, and an inner layer comprising a dielectric material. The cut feature extends above a top surface of the gate structure.

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate containing a first semiconductor material, a source region and a drain region in the semiconductor substrate, a gate electrode positioned in a lateral direction between the source region and the drain region, and a semiconductor layer positioned on the semiconductor substrate. The semiconductor layer contains a second semiconductor material that differs in composition from the first semiconductor material. The gate electrode includes a first section positioned in a vertical direction over the semiconductor layer and a second section positioned in the vertical direction over the semiconductor substrate.

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

Abstract: A method of manufacturing a lateral transistor is described. The method includes providing a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate. A gate layer is formed over the dielectric layer. A photoresist layer is applied over the gate layer. The photoresist layer is opened by lithography to form a first opening of a first opening size in the photoresist layer. The first opening is transferred into a second opening of a second opening size, the second opening being either formed in the photoresist layer or in an auxiliary layer. A body region is formed in the semiconductor substrate by dopant implantation. Further the gate layer is structured to form a gate edge. An overlap between the structured gate layer and the body region is controlled by an offset between the first opening size and the second opening size.

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

Abstract: A display apparatus includes a substrate, a display unit disposed on the substrate, an insulating layer disposed on the substrate, a power supply wire disposed on the insulating layer outside the display unit, and a cladding layer. The display unit includes a pixel circuit and a display element electrically connected to the pixel circuit. The insulating layer extends from the display unit to an edge of the substrate. The power supply wire is electrically connected to the display element and includes an alignment pattern that exposes at least a portion of the insulating layer. The cladding layer covers an inner surface of the alignment pattern and contacts the at least a portion of the insulating layer.

Abstract: A semiconductor device includes a gate structure that is formed upon and around a channel fin. The device further includes a source or drain (S/D) region connected to the fin. A spacer liner is located upon a sidewall of the S/D region facing the gate structure. An air-gap spacer is located between the gate structure and the spacer liner. A spacer ear is located above the air-gap spacer between the gate structure and the spacer liner. The spacer ear may be formed by initially forming an inner spacer upon a sidewall of the gate structure and forming an outer spacer upon the inner spacer. The outer spacer may be recessed below the inner spacer and the spacer ear may be formed upon the recessed outer spacer. Subsequently, the inner spacer and outer spacer may be removed to form the air-gap spacer while retaining the spacer ear.