Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine a historical discharge rate (dh) from multiple discharge rates a battery of an information handling system (IHS) while the IHS operates on electrical power provided by the battery; receive a current discharge rate (dc) of the battery; determine a full charge capacity correction factor value (Cfcc) associated with the battery; determine a weighting factor (?); determine a difference between a full charge capacity value (FCC) and Cfcc; determine ?·dh; determine (1??)·dc; determine a sum of dh·? and dc·?; determine a quotient value of FCC?Cfcc and ?·dh+(1??)·dc; scale the quotient value based at least on a relative state of charge of the battery to determine an estimated time remaining for the IHS to operate on the electrical power provided by the battery; and display the estimated time remaining.

Abstract: An integrated circuit (IC) test engine generates single cycle test patterns for testing for candidate faults and/or defects of a first set of static faults and/or defects of an IC design. A diagnostics engine receives single cycle test result data characterizing application of the single cycle test patterns to a fabricated IC chip based on the IC design and fault-simulates a subset of the single cycle test patterns against a fault model that includes multicycle faults and/or defects utilizing sim-shifting to diagnose a second set of static faults and/or defects in the fabricated IC chip that are only detectable with multicycle test patterns. The diagnostics engine further scores candidate faults and/or defects in the first set of static faults and/or defects and the second set of static faults and/or defects for applicable test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.

Abstract: Aspects described herein relate to mask synthesis using design guided offsets. A target shape on an image surface to be fabricated using a mask based on a design of an integrated circuit is obtained. Rays are generated emanating from respective anchor points. The anchor points are on a boundary of the target shape or a boundary of a mask shape of the mask. For each ray of the rays, a distance is defined between a first intersection of the respective ray and the boundary of the target shape and a second intersection of the respective ray and the boundary of the mask shape. An analysis is performed by one or more processors, where the analysis is configured to modify the distances based on an error between the target shape and a resulting shape simulated to be on the image surface resulting from the mask shape.

Abstract: Provided are a method and a system for optimizing charging and discharging behaviors of a BESS based on a SOH, relating to charging and discharging optimization. The number of cycles of the battery pack and corresponding DODs are obtained based on the curve of the SOC of the battery pack. Then, the SOH of the battery pack is obtained. A charging index sequence and a discharging index sequence of battery packs are obtained based on the SOH, the SOC and a charging and discharging state of the battery pack. The optimal number of the charging and discharging battery packs and optimal DODs are determined. Charging and discharging tasks are carried out according to the charging and discharging index sequences of the battery packs based on the optimal number of the charging and discharging battery packs and the optimal DODs.

Abstract: A method of designing a 3D Integrated Circuit, the method including: partitioning at least one design into at least two levels, a first level and a second level; providing placement data of the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; and performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.

Abstract: A parallel analog circuit automatic optimization method based on genetic algorithm and machine learning comprises global optimization based on genetic algorithm and local optimization based on machine learning, with the global optimization and the local optimization performed alternately. The global optimization based on genetic algorithm utilizes parallel SPICE simulations to improve the optimization efficiency while guaranteeing the optimization accuracy, combined with parallel computing. The local optimization based on machine learning establishes a machine learning model near the global optimal point obtained by the global optimization, and uses the machine learning model to replace the SPICE simulator, thus reducing the time costs brought by a large number of simulations.

Abstract: A process proximity correction method is performed by a process proximity correction computing device which performs a process proximity correction (PPC) through at least one of a plurality of processors. The process proximity correction method includes: converting a target layout including a plurality of patterns into an image, zooming-in or zooming-out the image at a plurality of magnifications to generate a plurality of input channels, receiving the plurality of input channels and performing machine learning to predict an after-cleaning image (ACI), comparing the predicted after-cleaning image with a target value to generate an after-cleaning image error, and adjusting the target layout on the basis of the after-cleaning image error.

Abstract: A method for identifying observation points for integrated circuit (IC) testing includes receiving a netlist for an IC that includes a first subcircuit and a second subcircuit; determining, from the netlist, one or more observation points, each determined observation point corresponding to an output node which provides observability, into at least the first subcircuit, of an effective number of gates above a specified threshold; and inserting a design for test element into a layout file of the IC at each determined observation point. Observation points can be determined by transforming the netlist into a node graph; assigning a same initial value to a value field of each node; and propagating values in the value fields of the nodes until all nodes with a succeeding edge have a value of zero in their value fields.

Abstract: A power sequence in a power-delivery (PD) mechanism (interaction between host system components and a charger) and a firmware sequence during power contract negotiation reduces the host system power consumption at or below the pSnkStdby power limit to improve user experience and battery life. The power sequence uses USB Type-C PD protocol and timing specification to implement a synchronous trigger or interrupt and interface mechanism. The synchronous trigger or interrupt and interface mechanism between a PD controller and an embedded controller firmware controls the power consumption dynamically during the boot flow sequence to be less than or equal to pSnkStdby power limit while implementing a predictable boot sequence and optimizing boot time. The power negotiating sequence is also applicable when a source (e.g., a charger) is connected to a SoC host system which is in active state (e.g., S0) and when there is an indication of low battery capacity.

Abstract: Electronic apparatuses according to embodiments of the present technology may include an enclosure having a lid. The enclosure may define a first cavity and a second cavity, and may include an enclosure battery. The apparatuses may include a first enclosure wireless charging coil extending about the first cavity. The apparatuses may include a second enclosure wireless charging coil extending about the second cavity. The apparatuses may include a first earbud having a first earbud battery and a first earbud wireless charging coil operably coupleable with the first enclosure wireless charging coil for wireless charging of the first earbud battery. The apparatuses may include a second earbud having a second earbud battery and a second earbud wireless charging coil operably coupleable with the second enclosure wireless charging coil for wireless charging of the second earbud battery.

Abstract: A non-transitory computer-readable medium storing codes that, when executed by a processor, cause the processor to perform operations of receiving full chip data including specific patterns of a first layout, extracting a representative pattern of the first layout from the full chip data, generating a vector of the extracted representative pattern, generating a first data set based on the generated vector, generating a machine learning model by performing machine learning with respect to the first data set, executing an optical proximity correction (OPC) with respect to the specific patterns of the first layout by using the machine learning model, and generating a second layout based on a result of executing the OPC may be provided.

Abstract: An electronic device includes a housing coupled to a display window, a battery and a plurality of inductive charging transmit coils coupled to the battery. The plurality of inductive charging coils are positioned within the enclosure to generate an inductive charging region that extends through the display window and across at least a portion of an exterior of the display window. Sensing circuitry is configured to sense a position of a stylus at the display window and a processor is configured to selectively engage and disengage one or more of the plurality of inductive charging transmit coils based on the sensed position of the stylus. The stylus receives power when it is positioned within the inductive charging window.

Abstract: A method including: simulating an image or characteristics thereof, using characteristics of a design layout and of a patterning process, determining deviations between the image or characteristics thereof and the design layout or characteristics thereof; aligning a metrology image obtained from a patterned substrate and the design layout based on the deviations, wherein the patterned substrate includes a pattern produced from the design layout using the patterning process; and determining a parameter of a patterned substrate from the metrology image aligned with the design layout.

Abstract: An electronic device is provided.

Abstract: A RF wireless charging enclosure configured to enable efficient wireless charging of a CE device in the enclosure while also allowing wireless communication of the CE device to devices outside the enclosure. In one example, time multiplexing is used such that the CE device is enabled to either be charged, or to communicate with a device outside the enclosure. In another example, frequency division is used such that the CE device is charged at a first frequency, and simultaneously communicates through the enclosure at a second different frequency.

Abstract: An electronic device comprises a processor, a charging port, and memory that stores program code. When the program code is executed by the processor, the electronic device charges a battery of the electronic device using the charging port when a charger is connected to the charging port, stops charging in response to detecting that the charging port is abnormal, and displays a first window on a display interface of the electronic device in response to detecting that the charging port is abnormal. The first window comprises a first prompt information and a second prompt information. The first prompt information is used to prompt that liquid intake exists in the charging port, and the second prompt information is used to prompt a user to exclude a liquid intake situation of the charging port.

Abstract: A process is disclosed that automatically creates a network-on-chip (NoC) very quickly using a set of constraints, which are requirements for the NoC. The process takes a set of constraints as inputs and produces a NoC with all its elements configured and a placement of such elements on the floorplan of the chip.

Abstract: A transformer structure may include a first coil having one or more turns, and a second coil having one or more turns. A turn of the one or more turns of the first coil may overlap a turn of the one or more turns of the second coil in a lateral direction substantially along the turn of the first coil and in a vertical direction substantially along the turn of the first coil. In some implementations, the transformer structure may be integrated in a semiconductor device.

Abstract: A method of charging a lithium-ion battery. It is assumed that the battery has a cooling system. A desired temperature profile for the battery during charging is determined. The charge current is pulse width modulated (PWM), as is the activation of the cooling system. During charging, various parameters of either or both of the PWM signals are adjusted such that the desired temperature profile is maintained.

Abstract: A wireless charging device includes a power source configured to generate a direct current (DC) voltage signal. Also, the wireless charging device includes a driver unit configured to receive the DC voltage signal and convert the DC voltage signal to a first alternating current (AC) voltage signal. Further, the wireless charging device includes a transmitting unit including a resonant capacitor and a resonant coil, coupled to the driver unit, wherein the transmitting unit is configured to receive and transmit the first AC voltage signal. Additionally, the wireless charging device includes a control unit configured to detect a receiver device based on a change in at least one of a capacitive voltage across the resonant capacitor and an inductive voltage across the resonant coil if the receiver device is positioned within a predetermined distance from the transmitting unit.