Abstract: A Centronics type interface comprising a switching circuit selectively outputting one of two input signals having a timing relationship such that only during the time one input signal is active, the other input signal is active according to the state of a select signal, a pulse generating circuit outputting a signal for a predetermined time from the rising edge of a signal outputted from the switching circuit, and a signal selecting circuit outputting one of the other input signals and a signal outputted from the pulse generating circuit, which can hold one input signal and the signal outputted from the signal selecting circuit in a desired timing relationship.

Abstract: A thin film transistor liquid crystal display having different size pixels wherein the channel width of the thin film transistors is proportional to the area or capacitance of the pixel to thereby equalize punch-through voltage, write time and hold time for the pixels and to eliminate flicker.

Abstract: In a circuit arrangement for steepening signal slopes of a digital signal in the form of a sequence of amplitude-discrete sampling values of an analog signal, the digital signal to be steepened is applied to a slope detector (1) which supplies a marking signal during the period in which a slope of the digital signal exceeds a given steepness value, which marking signal marks the sequence including the slope of the digital signal to be steepened, while a delay circuit (5) is provided in which the digital signal and the marking signal are delayed by a fixed period of time whose duration is longer than the maximum period of the sequences to be steepened, and a FIFO memory (6) is provided into which the amplitude value of the digital signal is entered at the instant of the end of the non-delayed sequence and from which memory the value is read at the instant of the start of the delayed sequence, and a sequence generator (8, 22) is provided which generates a steepened signal while taking account of the delayed dig

Abstract: A polarizing wavelength separating optical element, PWS, in the form of a flat panel causes each of a plurality of polychromatic optical beams from a source, entering at one surface and transmitted to the other surface, to be converted with high conversion efficiency into beams circularly polarized, spectrally separated and spatially separated. The input optical beams are identical and in the form of a linear periodic array illuminating the PWS element. Output circularly polarized beams are spatially separated by a variable distance and have separated wavelengths that can be in any order: ascending, descending or random. The PWS is made of a periodic array of cells whose period is identical to that of the optical source. Each cell comprises a plurality of subcells. One subcell functions as a broadband reflector, while each of the remaining subcells functions as a polarizing wavelength selective reflector.

Abstract: A variable pulse width precision pulse generator includes a constant current source for producing a number of different constant currents; a charge storage device whose voltage output is proportional to the charge stored; and gating means responsive to an input signal for controlling the time during which the constant current source charges the charge storage device to produce a ramp voltage; a first comparator responsive to the voltage ramp for detecting a first level of the ramp; a second comparator responsive to the voltage ramp for detecting a second level of the ramp; and logic means responsive to the comparators for providing a precision pulse during the presence of the input signal between the occurrence of the detection of the first and second levels of the ramp by the comparators.

Abstract: A transmission line driver circuit (10) includes a signal input (12). A first capacitor (28) stores a first voltage level corresponding to a first of two possible bit values of an input signal. A second capacitor (44) stores a second voltage level corresponding to a second of the possible bit values. First and second voltage supply sources (24, 42) are selectively and respectively coupled to the first and second capacitors (28, 44) for recharging these capacitors to their respective voltage levels. A transmission line (50) is coupled to an output of a switching circuit. The switching circuit is operable to couple the first capacitor (28) to the switching circuit output (34) in response to receiving an input signal of a first bit value. The switching circuit is further operable to couple the second capacitor (44) to the output (34) in response to receiving an input signal of a second bit value. The bit value is thereby propagated onto the transmission line (50).

Abstract: An active filter comprises a differential-type voltage-controlled current source. A first resistor is connected between the first input terminal of the voltage-controlled current source and a first signal source. A second resistor is connected between the second input terminal of the voltage-controlled current source and the second signal source (or the output terminal of the voltage-controlled current source). The incremental transfer conductance gm of the filter becomes smaller by R.sub.2 /(R.sub.1 +R.sub.2) compared to that of an active filter which does not contain the first and the second resistors of the active filter of the invention, where R.sub.1 and R.sub.2 are resistance values of the first and the second resistors, respectively.

Abstract: Prior art single FET switches suffer the disadvantage of uncertainties in the turning on and off thereof due to the high back bias voltage required. In the present system, by using a dual FET configuration, with the respective source regions of the FETs connected at a common node and a floating bias voltage source connecting the common node to the respective gate regions of the dual FET, a switching circuit which is capable of handling higher voltages and whose dB compression stays constant is provided. Since the dual FET circuit is symmetrical, depending on the polarity of the biasing voltage, the drain and the source regions are interchangeable.

Abstract: An absolute position detecting device in which the number of revolutions of a drive shaft adapted to drive an object to be controlled is counted with a counter for detecting an absolute position of the object. When a predetermined point on the object returns to an initial position after making one or more revolutions, the drive shaft is returned to an initial rotational angular position. A data rewriting operation is performed to rewrite, as necessary, the count value of the counter into a value obtained by subtracting a count value therefrom which is obtained during the one or more revolutions of the predetermined point.

Abstract: A gate circuit includes an N-channel and a P-channel insulated gate field-effect transistor whose parallel-connected drain-source paths constitute an analog signal gate and a control circuit, connected to the respective gate electrodes, to turn on and/or turn off the two field-effect transistors. In order to handle signals whose voltage value is higher than the maximum permissible drain-source voltage in the on-state of the N-channel field-effect transistor, means are provided, for turning on the N-channel field-effect transistor at least at a drain-source voltage below a predetermined value. In an embodiment of the invention the means include delay means coupled to the control circuit for turning on the N-channel field-effect transistor with a delay relative to the P-channel field-effect transistor. In another embodiment of the invention the means include switching means arranged in series with the analog signal gate, for temporarily connecting the signal gate to at least one auxiliary voltage.

Abstract: A differentiator circuit for sampled analog input currents comprises a first current memory cell including a capacitor (C2), a switch (S2), a transistor (T2) and a transistor (T3) and a second current memory cell including a capacitor (C1), a switch (S1) and a transistor (T1). During one portion (.phi.1) of each sampling period the input current (i) minus the current produced by the transistor (T1), which acts as a current source when switch (S1) is open, together with appropriate bias currents to allow bi-directional input currents to be handled, is fed via a switch (S3) to the first current memory cell. During another portion (.phi.2) of each sampling period the input current plus an appropriate bias current is fed to the input of the second current memory cell. The switches (S3) and (S2) are open so transistor (T2) acts as a current source providing an output via switch (S4) at an output (17) in addition to the output (15).

Abstract: A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked half-latch (32) is responsive to a first clockk phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch (34) is responsive to a second clock phase signal for transferring binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The pull-up circuit is responsive to the binary output signal and the input complement signal for generating an output complement signal.

Abstract: A multi-level potential generating circuit that brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential.The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage.

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirection bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches.

Abstract: BiCMOS circuits are disclosed which achieve high speed operation under a wide range of loading conditions. The circuits are capable of providing a full output voltage swing and dissipate virtually no static power. The BiCMOS circuits are implemented using both CMOS and bipolar transistors. The circuits use their output signal to control the CMOS transistors that overcome bipolar output drops for full swing operation. The same fundamental CMOS and bipolar configurations can be applied to implement complex and simple logic functions such as NAND, NOR, AND, or OR operations.

Abstract: A liquid crystal color display provides a transmitted light output that is of one or more colors, black, and/or white, as a function of the color of the incident light input and controlled energization or not of respective optically serially positioned liquid crystal color layers and/or multicolor composite liquid crystal color layer(s) in the display. In one case, the display includes a plurality of liquid crystal color layers, each being dyed a different respective color, and apparatus for selectively applying a prescribed input, such as an electric field of a given voltage level or frequency, to a respective layer or layers or to a portion or portions thereof. Each liquid crystal layer includes plural volumes of operationally nematic liquid crystal material in a containment medium that tends to cause an alignment of the liquid crystal structure and, thus, pleochroic dye included or mixed with the liquid crystal material in each layer to absorb light.

Abstract: Fast switching, high-contrast light valves and light valves which function for multi-level, gray-scale production are provided. Light valves of this invention employ two or more low-tilt, chiral smectic liquid crystal cells which are half-wave plates. Bistable FLC cells or FLC cells having smectic A* materials which display a field dependent tilt angle can be used. The FLC cells of exemplary device configurations are positioned sequentially along a light path through the device with the optic axes of the sequential FLC cells rotating in opposite directions upon application of a driving electric field thereacross. Light valves employing smectic C* and smectic A* liquid crystal cells are provided.

Abstract: A Hall element switching system which provide clean switching and wherein the system operate and release points are the same. The system includes a Hall element, first and second comparator circuits and a feedback circuit. The Hall element is the sensing part of the system and produces a voltage output which is proportional to the strength of the magnetic field impinging thereon. The output of the Hall element controls the switching of the first and second comparator circuits. The second comparator circuit, in turn, controls the output of the feedback circuit. The feedback circuit output is connected to the input of the first comparator circuit and can be at one of three levels. The feedback circuit by being connected to the input of the first comparator circuit causes a shift in the operate and release points of the first comparator circuit. The output of the first comparator circuit is the system output.

Abstract: A power-on reset circuit, which includes a fully symmetrical flip-flop in the path of propagation of the reset pulse. The two outputs of the flip-flop are combined together, so that propagation of the pulse can occur as soon as the flip-flop has stabilized in either of its possible stable states. However, a feedback connection cuts off any further propagation through this path once a power-on reset pulse has been issued. Thus, this circuit is extremely stable, and will not issue further power-on reset pulses even if hit with a very severe power glitch.

Abstract: A liquid crystal display comprises as liquid crystal panel having a liquid crystal layer disposed between electrode layers, polarizers disposed at both sides of the panel, and a solid birefringent film having the maximum refractive index direction varying with its depth and disposed at at least one side of the liquid crystal panel between the polarizers. The solid birefringent film conpensates the dependence of the polarization characteristic on wave length, thus being capable of obtaining either a monochrome display or a display having an extremely low coloration.