Abstract: A power supply signal conditioning system includes a power supply, one or more loads, and a drive-sense circuit (DSC). The power supply is operably coupled to one or more loads. When enabled, the power supply configured to output a power supply signal having a DC (direct current) voltage component and a ripple voltage component that is based on conversion of an AC (alternating current) signal in accordance with generating the power supply signal. The DSC is operably coupled to the power supply. When enabled, the DSC is configured simultaneously to sense the power supply signal and, based on sensing of the power supply signal, adaptively to process the power supply signal in accordance with reducing or eliminating the ripple voltage component of the power supply signal to generate a conditioned power supply signal to service the one or more loads.

Abstract: Systems, apparatuses, methods, and computer program products are disclosed for managing operation of a distributed system that provides computer-implemented services. An example method includes collecting, via an out-of-band stream, sensor data from a plurality of temperature sensors positioned to infer temperatures of components of a distributed system. The example method further includes inferring, using the inferred temperatures, power consumption rates for performing respective actions with each of the components. The method further includes obtaining an action request and selecting, based on the inferred power consumption rates, a particular component of the components to perform an action to service the action request, the selection being made with a preference to reduce power consumption for performance of the action.

Abstract: In an approach to optimizing dynamic system reconfiguration, a computer receives an active system configuration and a target system configuration from a system administrator, where the target system configuration includes two or more logical partitions. A computer determines one or more reconfiguration actions required to transform the active system configuration to the target system configuration. A computer generates a dependency graph based on the determined reconfiguration actions. A computer divides the dependency graph along the two or more logical partitions. A computer sorts the determined reconfiguration actions by associated dependencies. A computer orders the determined reconfiguration actions based on a priority of each of the two or more logical partitions. A computer runs a first simulation of the determined reconfiguration actions for each of the two or more logical partitions. A computer performs the determined reconfiguration actions for each of the two or more logical partitions.

Abstract: Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.

Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.

Abstract: An Ethernet power supply receives a DC voltage through a bus positive terminal and a bus negative terminal, and is coupled to a load device. The Ethernet power supply includes a first control module and a second control module. The first control module provides a first control signal through the bus negative terminal to confirm whether the load device is a valid load. The second control module is used to connect or disconnect a coupling relationship between the bus positive terminal and the first control module according to whether the load device is connected to the Ethernet power supply.

Abstract: Dynamic determination of a leader node during installation of a multiple node environment is implemented using a shared device and a messaging framework. The leader node is responsible for managing installation of all shared resources. When installation of a multiple node environment is initiated, each node runs a local boot script that governs its local boot process. Each node posts status updates of its boot operations to the messaging framework. Each node also dynamically determines whether it is the leader node by checking the messaging framework to learn whether installation of any of the shared resources has been started. If installation of the shared resources has not started, the node attempts to obtain a lock on the shared device. The node that obtains the lock on the shared device is the leader node. The leader node posts status updates related to installation of the shared resources to the messaging framework.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a multiprocessor boot flow for a faster boot process are described. In one embodiment, a system includes a hardware processor comprising a processor core, a cache coupled to the hardware processor, storage for hardware initialization code, and a controller circuit to initialize a portion of the cache as memory for usage by the hardware initialization code before beginning execution of the hardware initialization code after a power on of the system.

Abstract: Systems and methods for managing a power budget are provided. The method includes designating, by a power budget manager implemented on at least one processor, each of one or more applications with an individual quality of service (QoS) designation, the one or more applications executable by the at least one processor, assigning, by the power budget manager, a throttling priority to each of the one or more applications based on the individual QoS designations, determining, by the power budget manager, whether a platform mitigation threshold is exceeded, and responsive to determining that the platform mitigation threshold is exceeded, throttling, by the power budget manager, processing power allocated to at least one application of the one or more applications based on the throttling prioritization.

Abstract: Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

Abstract: Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.

Abstract: For a neural network inference circuit that executes a neural network including multiple computation nodes at multiple layers for which data is stored in a plurality of memory banks, some embodiments provide a method for dynamically putting memory banks into a sleep mode of operation to conserve power. The method tracks the accesses to individual memory banks and, if a certain number of clock cycles elapse with no access to a particular memory bank, sends a signal to the memory bank indicating that it should operate in a sleep mode. Circuit components involved in dynamic memory sleep, in some embodiments, include a core RAM pipeline, a core RAM sleep controller, a set of core RAM bank select decoders, and a set of core RAM memory bank wrappers.

Abstract: Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.

Abstract: Embodiments of this application disclose an application processor wakeup method and apparatus applied to a mobile terminal. In the method, whether the mobile terminal is in a preset first state is first detected. After it is determined that the mobile terminal is in the preset first state, a to-be-reported instruction that needs to be reported to an application processor and the priority of the to-be-reported instruction are obtained. When the priority of the to-be-reported instruction is higher than a preset priority, the to-be-reported instruction is reported to the application processor, to wake up the application processor, so that the application processor performs a corresponding operation.

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.

Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.

Abstract: Techniques are provided for detecting and mitigating electromagnetic signal attacks. One method comprises monitoring a processing environment having an electrical component for a signal having one or more signal characteristics that satisfy one or more signal criteria, wherein the one or more signal criteria are determined based on one or more wave characteristics of one or more electromagnetic waves emitted by operation of the electrical component; and automatically adjusting an operating frequency and/or an operating phase of the electrical component in response to detecting the signal having the one or more signal characteristics that satisfy the one or more signal criteria. The automatically adjusting may be performed by a basic input/output system. The electrical component may comprise a processor and the automatically adjusting may activate an overclocking feature of the processor.

Abstract: Provided is a non-transitory computer-readable recording medium that stores a control program causing a computer to execute a process, the process including determining whether first microcode stored in a first area of a storage device supports a processor, and when the first microcode does not support the processor, decompressing one of multiple sets of compressed second microcode stored in a second area of the storage device into the first area.

Abstract: A semiconductor device which is a processor includes a plurality of first power supply regions in each of which a functional module having a predetermined function is arranged and to which a power supply voltage is individually supplied, a setting unit configured to specify an order of supplying the power supply voltage in the plurality of first power supply regions, and a power controller configured to supply the power supply voltage to the plurality of first power supply regions in accordance with the order specified by the setting unit.

Abstract: Power consumption can be reduced by preventing a memory image from being destaged to a nonvolatile memory device. For example, a system can determine, subsequent to a computing device being in a first power mode and having a memory image stored in a first nonvolatile memory device that performs a caching function, that the computing device is in a second power mode that is a higher power mode than the first power mode. The system can, in response to determining that the computing device is in the second power mode, generate a first command to store the memory image in a volatile memory device and prevent the memory image from being stored in a second nonvolatile memory device. The system can, in response to generating the first command, store the memory image in the volatile memory device.