Abstract: A method and system for rewriting data in a non-volatile memory of the type which requires a comparatively long period of time for the rewriting of stored data. The occurrence of an interruption in power can be detected on the basis of the content of the non-volatile memory, and detection takes place after the resumption of power even if the interruption in power takes place during the rewriting operation. The non-volatile memory is provided with a flag area in which information indicating the initiation of a modification is written prior to the rewriting operation, and in which information indicating the termination of a modification is written after the rewriting operation, whereby an interruption in power which has occurred during rewriting is readily detected by reading out the information from the flag area after the restoration of power.

Abstract: Apparatus for and method of searching a data base using variable search criteria. The data base consists of a set of files or portions thereof. Each file is divided into a number of records whereby all records of a given file have the same format but the records of different files may have different formats. A field format register is used to define the format of the records within a given file. The field format register specifies the location and width of each field within a record. To perform a search, a field-by-field comparison of each record is made to a reference word. The comparison yields a less than, equal to or greater than result for each field of each record. A field comparison register describes the expected result of the field-by-field comparison. A given field is designated true if the comparison yields the expected result specified for that field in the field comparison register.

Abstract: A high speed shift register device includes first and second shift registers. Odd numbered bits of a word are stored in the first shift register and even numbered bits of the word are stored in the second shift register. The first shift register is clocked by a clock signal, and the second shift register is clocked by the complement of the clock signal. The outputs of the first and second shift registers are alternately shifted by means of a multiplexer to an output conductor. A control input of the multiplexer is connected to the clock input. Data is shifted out of the multiplexer at a rate which is twice the normal shifting rate of each of the first and second shift registers.

Abstract: A microprogrammed control system capable of overlapping the fetch and execution of microinstructions even when a conditional jump microinstruction is being executed. The control system comprises a pipeline register for storing the microinstruction currently being executed. The system also includes address circuitry for forming an "ordinary address" which is one greater than the address of the microinstruction in the pipeline register and for forming at least one "jump address" of a microinstruction occurring elsewhere in the program. A conditional jump microinstruction identifies a jump address for the microinstruction to be executed next, which jump address is only valid after the condition identified by the conditional jump instruction is tested and indicates that the jump address is to be used. Otherwise, the next microinstruction has an ordinary address.

Abstract: A cache memory organization is shown using a miss information collection and manipulation system to insure the transparency of cache misses. This system makes use of the fact that the cache memory has a faster rate of operation than the rate of operation of central memory. The cache memory consists of a set-associative cache section consisting of tag arrays and control with a cache buffer, a central memory interface block consisting of a memory requester and memory receiver together with miss information holding registers section consisting of a miss comparator and status collection device. The miss information holding register section allows for an almost continual stream of new requests for data to be supplied to the cache memory at the cache hit rate throughput.

Abstract: In this apparatus for dynamically translating virtual memory addresses to real memory addresses, a master system page table maintained in a memory associates real memory addresses with their corresponding system virtual memory addresses. This table is organized with each virtual memory address stored in it at an index location which is a smaller value formed as a predetermined function of the virtual memory address value. The translator forms the index from the virtual memory address according to the function, enters the table with it, and extracts the corresponding real memory address. In a preferred embodiment, every process (i.e., job) may reference any address in any segment of a process virtual address space, and a dedicated mechanism converts such a process virtual address reference to a system virtual memory address, which then is converted to the real memory address.

Abstract: A microcomputer which controls a device or apparatus in accordance with a control program prestored in a Read Only Memory included in the microcomputer, further comprises a Random Access Memory for storing parity bits of the control program. The data indicative of the control program prestored in the Read Only Memory are read out in sequence and are fed to a central processing unit of the microcomputer so that parity bits of the prestored data are produced and then stored in the Random Access Memory. The parity bits stored in the Random Access Memory are used to check whether the prestored data are correct or not.

Abstract: In an interrupt control system for a data processing unit for microprogram control including a processor constructed dividedly between an arithmetic unit and a control unit, a signal representing the absence or presence of an interrupt request to be performed is applied to the control unit so that said control unit reads a microprogram for the interrupt processing from a memory in response to said signal, and said arithmetic unit judges an interrupt source on the basis of the microprogram read out from said memory and performs processing in accordance with the interrupt source.

Abstract: To ensure continuous uninterrupted operation of an a-c line voltage-energized microcomputer in the event of a power failure, the line voltage is effectively sensed and in response to a substantial reduction thereof battery power is supplied to the microcomputer before such a reduction can adversely affect the operation of the microcomputer.