Abstract: A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.

Abstract: An apparatus for processing data of a non-volatile memory includes a non-volatile memory having a plurality of blocks, an operation processing unit which, when a write operation is requested from a user, writes data in the plurality of blocks, and a block managing unit which collectively converts the plurality of blocks, where the data is written, to a plurality of data blocks and manages statuses of the plurality of blocks to correspond to an operation process performed by the operation processing unit.

Abstract: A method, information processing system, and computer program storage product for managing disk failures in a disk array. At least one disk in a first disk array is determined to have failed. The first disk array only accesses data by reading an entire stripe that is distributed across multiple disks in the first disk array. A number of spare disks are selected that is equal to a number of disks making up the first disk. A second disk array is created from the number of disks that has been selected. Data is acquired from the first disk array by reading at least one entire stripe from the first disk array. A corresponding stripe comprising the data from each respective stripe that has been acquired is written to the second disk array.

Abstract: A method, apparatus and program product enable scalable bandwidth and memory for a system having processor with directly attached memory. Multiple memory expander microchips provide the additional bandwidth and memory while in communication with the processor. Lower latency data may be stored in a memory expander microchip node in the most direct communication with the processor. Memory and bandwidth allocation between may be dynamically adjusted.

Abstract: A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.

Abstract: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state.

Abstract: A temporary file is identified. The temporary file includes a data block containing a first file image. A determination is made whether the temporary block has been included in a previous snapshot. Responsive to receiving a modification of the temporary block that has been included in the previous snapshot, a modified first image is created. The modified image is stored in the original file block, and the original image is copied to a newly allocated block. The original first block is updated to include a reference to the second block.

Abstract: Upon retrieving, after occurrence of replacement of a first cache, move out (MO) data that is a write back target, a second cache determines, based on data that is set in a control flag of a register, whether a new registration process of move in (MI) data with respect to a recording position of the MO data is completed. Upon determining that the new registration process is not completed, the second cache cancels the new registration process to ensure that a request of the new registration process is not output to a pipeline.

Abstract: This invention aims to optimize an entire storage system by equalizing the access counts in appropriate units. When migrating data in pool volumes to equalize the data access counts, which data migration—data migration in units of pages or data migration in units of volumes—is most appropriate is judged based on the information stored in an access information table storing access information, which is the information about the access counts for the data stored in the disk drives and, based on the judgment, data is migrated in units of pages or volumes so that the data access counts are equalized among groups. The data migration is repeated until the data access counts are equalized among the groups.

Abstract: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. Each data file is uniquely identified in a file directory, which points to entries in a file index table (FIT) of data groups that make up the file and their physical storage locations in the memory.

Abstract: A method and apparatus for controlling discontinuous transmission and reception are disclosed. A Node-B schedules an offset for discontinuous transmission (DTX) and/or discontinuous reception (DRX) for a user equipment (UE) and sends the offset to the UE. The UE then shifts the DTX and/or DRX pattern based on the received offset. The UE may modify the offset based on the transmission time of an activation command for DTX and DRX. The UE may modify an offset for DTX and DRX to shift the DTX pattern and DRX pattern when the UE receives downlink data or transmits uplink data based on a sub-frame number at the time of the downlink reception and uplink transmission.

Abstract: One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.

Abstract: In one embodiment, a computer system comprises a host machine comprising a plurality of compute resources, at least one secure memory location coupled to the host machine, wherein the secure memory location stores host machine configuration data, and a virtual machine host module coupled to the host machine. The virtual machine host module comprises logic to map a path to the secure memory location, receive a signal indicating whether a first virtual machine guest should be permitted access to the host machine configuration data, and associate at least a portion of the host machine configuration data with the first virtual machine guest when the when the signal indicates that the first virtual machine guest should be permitted to access the configuration data.

Abstract: A disk storage system containing a storage device having a record medium for holding the data, a plurality of storage sub-systems having a controller for controlling the storage device, a first interface node coupled to a computer using the data stored in the plurality of storage sub-systems, a plurality of second interface nodes connected to the storage sub-systems, a switch connecting to a first interface node and a plurality of second interface nodes to perform frame transfer therebetween based on node address information added to the frame. The first interface node has a configuration table to store structural information for the memory storage system and in response to the frame sent from the computer, analyzes the applicable frame, converts information relating to the transfer destination of that frame based on structural information held in the configuration table, and transfers that frame to the switch.

Abstract: Systems, methods, apparatus and software can be implemented to detect possible instances of memory corruption. By analyzing memory blocks stored in a memory, provided in a snapshot file, or provided in a core dump, implicit and/or explicit contingency chains can be obtained. Analysis of these contingency chains identifies potential memory corruption sites, and subsequent verification provides greater confidence in the identification.

Abstract: This invention provides a specified retention date within a data set that is locked against deletion or modification within a WORM storage implementation. This retention date scheme does not utilize any proprietary application program interfaces (APIs) or protocols, but rather, employs native functionality within conventional file (or other data containers, data sets or block-based logical unit numbers) properties available in commonly used operating systems. In an illustrative embodiment, the retention date/time is calculated by querying the file's last-modified time prior to commit, adding the retention period to this value and thereby deriving a retention date after which the file can be released from WORM. Prior to commit, the computed retention date is stored in the file's “last access time” property/attribute field, or another metadata field that remains permanently associated with the file and that, in being used for retention date, does not interfere with file management in a WORM state.

Abstract: A method for managing a virtual memory system configured to allow multiple page sizes is described. Each page size has at least one table associated with it. The method involves maintaining entries in the tables to keep track of the page size for which the effective address is mapped. When a new effective address to physical address mapping needs to be made for a page size, the method accesses the appropriate tables to identify prior mappings for another page size in the same segment. If no such conflicting mapping exists, it creates a new mapping in the appropriate table. A formula is used to generate an index to access a mapping in a table.

Abstract: A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.

Abstract: Techniques are provided for performing multi-pass erase. An erase command is received at a storage area network (SAN) switch in a storage area network. The erase command is associated with a block of data on a target device. A virtual initiator is determined for performing the erase command on the block of data. Multiple bit patterns are generated using a multi-pass erase algorithm. The multiple bit patterns are generated for writing over the block of data on the target device. Repeated writes are performed over the block of data using the bit patterns. The block of data is repeatedly overwritten to remove remanence of the block of data on the target device.

Abstract: A device and method for connection to a host and transferring data between the host and data storage assembly. The device is preferably a storage system which initializes a logical unit (LUN) in the storage assembly. A persistent memory stores a data representation of clean areas in the LUN. The storage system receives data to be written from the host to a destination area in the LUN, and determines if the destination area in the LUN is a clean area or a dirty area as indicated in the persistent memory. The storage system effects a snapshot copy of data from the destination area in the LUN to an archive storage device of the storage assembly only if the destination area is not entirely a clean area. Bandwidth is likewise reduced in LUN copy and reconstruction operations.