Abstract: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

Abstract: An assembly for an LSI test supplies a test signal output from an LSI tester to a target LSI to be tested and outputs, to the LSI tester, a test result signal generated by processing of the target LSI performed in accordance with the test signal. The assembly for an LSI test includes: a peripheral circuit coupled to the target LSI and allowing the target LSI to operate in the same manner as in the application environment; and a printed circuit board on which the peripheral circuit is mounted.

Abstract: The test method for a semiconductor integrated circuit includes a multi-cycle test step and a single-cycle test step. In the multi-cycle test step, a data-read side flipflop holds data according to a clock enable signal to test a multi-cycle path. In the single-cycle test step, no data is captured for the multi-cycle path.

Abstract: An ECC circuit has an error correction function of N (N is a natural number) bits for output data of a memory cell array. A BIST circuit reads background data out of test target addresses, and writes/reads inverted data of the background data in at least a part of the testing target addresses. An N+1 bit error detection circuit outputs a signal indicative of test NG (defective product) when a total of error bit numbers n1 and n2 detected by the ECC circuit during first and second readings exceeds N.

Abstract: A method for managing testing of test material is disclosed. An electronic traveler associated with the test material is identified. The test materials are tested as specified by the electronic traveler. Test results from the tests are recorded onto the electronic traveler.

Abstract: An apparatus (1) for testing a memory module (2) suitable for exchanging electrical signals with a motherboard (10) contains a device (8a–8k) suitable for detecting the operating state of at least one semiconductor chip (26a–26m) of the module, which device comprises a first set of signal lines (8a–8k), a microcontroller (3) with a memory device (32) for storing the operating state, said microcontroller being electrically connected to the signal lines (8a–8k), a clock generator (5) suitable for generating an operating clock, said clock generator being electrically connected to the microcontroller (3), and a signal connection (13) suitable for communicating a signal for controlling access to the memory module (2) between the circuit board arrangement (10) and the microcontroller (3) and for communicating to the microcontroller (3) a signal for initiating a process of detecting the operating state.

Abstract: A method and apparatus for detecting errors in a memory includes generating a first check word based on incoming data and generating a second check word based on stored data. The method includes comparing the first check word to the second check word, generating a comparison result, and indicating a failure based on the comparison result.

Abstract: A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.

Abstract: A system and method thereof for semiconductor test management. A first computer generates a new gating rule and transmits the new gating rule. A second computer receives the new gating rule via a network, acquires a test result, carries the test result into the new gating rule to generate an advisory report. In which, the test result comprises a test value corresponding to a test attribute, the new gating rule determines a final advisory when the test value satisfies a specific condition comprising the test attribute, and the advisory report comprises the final advisory.

Abstract: The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect, a test circuit being provided in order to receive defect data from one or a plurality of connectable memory modules to be detected, the test circuit being configured in such a way as to store the received defect data depending on addresses assigned thereto in the memory unit.

Abstract: A self-calibrating strobe signal generator for a BIST circuit responds to an edge of an input strobe signal by generating corresponding edges of first and second strobe signals separated in time by a target delay specified by input data. The strobe signal generator includes a multiplexer, a delay circuit and a controller. The multiplexer normally provides the input strobe signal as a multiplexer output signal to the delay circuit which generates edges in each of the first and second strobe signals in response to each edge in the multiplexer output signal with a programmable delay between corresponding first and second strobe signal edges.

Abstract: A method for scheduling a decoding process of coded data blocks transmitted over a link in a communication network. According to the method the coded data block is stored in a queue (71) if all decoders of a cluster (72) of iterative parallel decoders are unavailable. When any of the decoders of the cluster (72) is available the first coded block of the queue (71) is moved to that decoder. Also, according to the method it is possible to combine a stored coded block with a retransmitted coded block, which is decoded with an increased probability for successful decoding. Also, the invention relates to a communication apparatus adapted for carrying out the method according to the invention.

Abstract: A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.

Abstract: A method of testing write enable lines of random access memory having at least one word having one or more write enable inputs for controlling write operations in the word, comprises, for a selected memory address, shifting a series of test bits through an addressed word via a first data input to the word, and for each test bit, performing a write operation to the word using a write enable test input derived from data outputs of the word or from a test write enable signal applied concurrently to each write enable input; and, after each write operation, comparing a last bit of the word against an expected value to determine whether there exists a defect in a write enable line.