Abstract: In order to suppress the effect due to electrons (holes) generated by incident light that cannot be prevented from entering only by means of light shielding, rather than the drain region 34 of a transistor, with respect to a majority carrier, a region 36 whose voltage is set to a value lower than the reference value of product of the voltage of a drain region and Q (unit electric charge) is provided, or a potential barrier is provided around the drain region. In such a configuration, by controlling the voltage of the periphery of the drain region 34 connected to a reflection electrode 30 to be in a floating state, photo carriers generated in the semiconductor substrate are caused to be hardly guided in the drain region 34.

Abstract: A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.

Abstract: A wiring board used for mounting an LED bare chip capable of firmly bonding the LED bare chip and improving yield. In a printed wiring board 2, a distance D between wiring patterns 81 and 85 disposed so as to oppose each other is the smallest at a position nearest to a center point (G) of an LED chip 14 disposed at a designed location, and increases with an increasing distance from the point G. In addition, pattern edges 83 and 87 of the wiring patterns 81 and 85 recede in the direction of widening the distance D as a distance from the center point G increases with respect to electrode edges 148 and 149 of the LED chip 14.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an inductively coupled etching apparatus. The high density plasma is set and controlled to isotropically contact particular regions of the inorganic material to allow for trimming and control of a critical dimension associated with the inorganic material.

Abstract: A power semiconductor component (2) has a semiconductor body with a front face (7) and a rear face (9). The front face (7) has a front-face metallization (8), which provides at least one first contact pad (11). A structured metal seed layer (14) is provided as the front-face metallization (8), is arranged directly on the semiconductor body, and has a thickness d, where 1 nm?d?0.5 ?m.

Abstract: A wiring substrate to which a semiconductor element 10 is connected, is a wiring substrate 20 comprised of a glass substrate with through-hole groups 20d, each group consisting of a plurality of through holes 20c extending from input surface 20a to output surface 20b and formed in a predetermined array, and conductive members 21 formed on respective inner walls of the through holes 20c in each through-hole group 20d so as to establish electrical continuity between input surface 20a and output surface 20b. A bump electrode 12 of semiconductor element 10 connected to the input surface 20a corresponds to each through-hole group 20d, conductive member 21, and conductive part 22 formed in a region covering the through-hole group 20d, and is connected so that a portion of the bump electrode 12 enters into an interior of each of the through holes 20c.

Abstract: In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of a boundary column of a second conductivity type material defines the boundary between the active region and the termination region. The active and termination regions include columns of first and second conductivity type material alternately arranged along a horizontal direction in a semiconductor region having top and bottom surfaces. At least one of the columns of the first conductivity type material in the termination region has a different width than a width of the columns of the first conductivity type material in the active region.

Abstract: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.

Abstract: Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

Abstract: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.

Abstract: Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition.

Abstract: A method is disclosed for fabricating an LED The method includes providing an LED chip having an epitaxial region comprising at least a p-type layer and an n-type layer, an ohmic contact formed on at least one of the p-type layer or the n-type layer, and a bond pad formed on the ohmic contact. The bond pad has a total volume less than about 3×10?5 mm3. The LED chip is bonded to a submount via thermocompression or thermosonic bonding.

Abstract: Semiconductor devices and methods for fabricating a semiconductor devices are disclosed. A disclosed method comprises: forming a first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate electrode functioning as a normal gate electrode; forming a source/drain region with a shallow junction by performing a first ion implantation process using at least one of the first spacers as a mask; forming second spacers on a sidewall of the first spacer and on sidewalls of the second gate electrode; forming a source/drain region with a deep junction by performing a second ion implantation process using the second spacers as a mask.

Abstract: A display device includes a substrate having a display region and a driver region; a gate line and a data line crossing each other to define a pixel region in the display region, the pixel region having a pixel electrode; an insulation layer between the gate line and the data line; a first thin film transistor in the display region; and a second thin film transistor having a first polarity and a third thin film transistor having a second polarity in the driver region, wherein the pixel electrode, the gate line and the gate electrodes of the first to third thin film transistors have a double-layer structure in which a metal layer is formed on a transparent conductive layer, and the transparent conductive layer of the pixel electrode is exposed through a transmission hole passing through the insulation layer and the metal layer in the pixel region.

Abstract: Methods are disclosed for improving organic thin-film transistor (OTFT) performance by acid doping of the semiconducting layer. The semiconducting polymer comprising the semiconductor layer is doped with an acid, especially a Lewis acid, either during or after polymerization of the polymer, but prior to application of the polymer onto the OTFT. Also disclosed are OTFTs having enhanced charge carrier mobility produced by these methods.

Abstract: An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.

Abstract: The present invention relates to a III-nitride semiconductor light-emitting device having high external quantum efficiency, provides a III-nitride compound semiconductor light-emitting device including an active layer generating light by recombination of electrons and holes and containing gallium and nitrogen, an n-type Al(x)ln(y)Ga(1-x-y)N layer epitaxially grown before the active layer is grown, and an n-type electrode electrically contacting with the n-type Al(x)ln(y)Ga(1-x-y)N layer, in which the n-type Al(x)ln(y)Ga(1-x-y)N layer has a surface which is exposed by etching and includes a region for scribing and breaking the device and a region for contact with the n-type electrode, and the surface of the region for scribing and breaking the device is roughened, thereby it is possible to increase external quantum efficiency of the light-emitting device.

Abstract: Heterostructure devices incorporate carbon nanotube technology to implement rectifying devices including diodes, rectifiers, silicon-controlled rectifiers, varistors, and thyristors. In a specific implementation, a rectifying device includes carbon nanotube and nanowire elements. The carbon nanotubes may be single-walled carbon nanotubes. The devices may be formed using parallel pores of a porous structure. The porous structure may be anodized aluminum oxide or another material. A device of the invention may be especially suited for high power applications.

Abstract: A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the at least one first and the at least one second memory elements.