Abstract: In an integrated circuit, a wraparound isolation region capable of sustaining a high blocking voltage to a substrate encloses a variety of high voltage or low voltage device.

Abstract: For a vertical DMOS power transistor or a high voltage bipolar transistor, an edge termination at the perimeter of the die surrounding the active transistor cells includes multiple spaced apart field rings. A trench is located between each adjacent pair of field rings and is insulated either by oxide formed on the sidewalls thereof or by an oxide filling. The insulated trenches allow the field rings to be very closely spaced together. Advantageously the trenches may be formed in the same process steps as are the trenched gate electrodes of the active portion of the transistor. This structure eliminates the necessity for fabricating thick field oxide underlying a conventional field plate termination, and hence allows fabrication of a transistor without the need for a field plate termination, and in which the multiple field rings are suitable for a transistor device having a breakdown voltage in the range of 20 to 150 volts.

Abstract: An injection control-type Schottky barrier rectifier, including: a semiconductor region having a first conductivity type; a first diffusion region, which is formed in the semiconductor region and which has a second conductivity type, the second conductivity type being different from the first conductivity type, for forming a depletion layer in the semiconductor region when a turn-off voltage is applied to the Schottky barrier rectifier; a second diffusion region, which is formed in the semiconductor region and which has the second conductivity type, for causing conductivity modulation in the semiconductor region when a turn-on voltage is applied to the Schottky barrier rectifier; a barrier electrode which is ohmically connected with the first diffusion region and which forms a Schottky junction with the surface of the semiconductor region which is opposite to the second diffusion region with respect to the first diffusion region; a gate insulator film formed on the surface of the semiconductor region between

Abstract: A contact structure and a method for fabrication is disclosed for a semiconductor device that includes a plurality of semiconductor regions along the surface of the device, each region having a top surface and at least a sidewall surface, where a first part of the semiconductor regions are of a first conductivity type and a second part of semiconductor regions are of a second conductivity type. Select dielectric spacers are formed along the sidewalls of the select semiconductor regions of first conductivity type while a refractory metal such as titanium, molybdenum or tungsten is used to form contact on the sidewalls of the semiconductor regions of second conductivity type. This structure is most advantageous in bipolar, CMOS and BiCMOS transistor structures as it allows the formation of the sidewall spacers on emitter/gate contacts while having local metal interconnects with the reactive metal on the sidewall of the select base/source/drain contacts.

Abstract: A base cell for a CMOS gate array is disclosed, which utilizes cutoff transistor isolation. The disclosed cell implements the cutoff transistor isolation by way of separate outer electrodes for the p-channel and n-channel sides, so that p-type and n-type diffused regions are disposed at the edges of the cell to be shared with adjacent cells. The disclosed cell further includes a pair of inner electrodes which extend over both the n-type and p-type active regions. This construction enables the use of cutoff isolation techniques, but also provides the ability to implement transmission gate style latches via the common complementary gate inner electrodes. Greater efficiency of silicon area, improved utilization, and reduced input loading and active power dissipation result from an integrated circuit incorporate the disclosed cells.

Abstract: At least one power output element made of an insulated gate semiconductor element, a surge protection element for an input electrode of the power output element, and a circuit element block for controlling the power output element, are formed on the same semiconductor substrate. A predetermined electrode of the power output element and one end of the surge protection element are connected to each other. In this state, first, second, and third electrode wiring layers are connected to an output terminal of the circuit element block, the other end of the surge protection element, and the input electrode of the power output element, respectively, and the first to third electrode wiring layers are formed separately from one another. In order to connect the first to third electrode wiring layers to each other, a fourth electrode wiring layer is formed thereon.

Abstract: A semiconductor device (10) has a thin-film transistor (TFT) formed in and around an opening (24) in a dielectric layer (22). A conductive layer (26) lines the opening sidewalls and serves as a gate electrode of the transistor. A conductive layer (30) is deposited over the gate electrode to form a source region (32), a channel region (36), and a drain region (34). The two conductive layers are separated by a gate dielectric (28). Because both the gate electrode and the channel region conform to the opening sidewalls and bottom, the entire channel region is under direct gate control. Device (10) may also include a conductive region, such as a gate electrode (15) of a bulk transistor, at the bottom of opening (24) and in electrical contact with the TFT gate electrode.

Abstract: A lower electrode of a capacitor for use in a semiconductor device includes a first semiconductor layer having a predetermined impurity concentration and a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer. As a result, intensification of an electric field at an end portion of the capacitor can be reduced. In addition, a word line is formed of a buffer layer and a main conductor layer to reduce a parasitic capacitance between the lower electrode of the capacitor and the word line.

Abstract: In a semiconductor integrated circuit, an amplifier FET and a gate bias FET, having the same structure as the amplifier FET and a total gate width smaller than that of the amplifier FET, are disposed close to each other. The gate bias FET is a constituent of a gate bias circuit for the amplifier FET, and the current determined by the drain current of the gate bias FET, first and second resistors respectively connected to drain and source of the gate bias FET, and a diode connected in series to the first resistor is applied to the amplifier FET as a gate bias voltage. In this structure, if the DC characteristic of the amplifier FET varies from chip to chip, the DC characteristic of the gate bias FET formed in the vicinity of and simultaneously with the amplifier FET also varies.

Abstract: A vertical double diffused MOSFET includes a gate electrode formed with a plurality of first open windows and at least one second open window connecting two of the first open windows. The first open windows are of a desired polygonal shape and have centers at lattice points of a square lattice provided in a first direction and a second direction orthogonal to the first direction with predetermined interval. The second open window takes in the form of slit having a predetermined width and arranged on a line connecting the center of one first open window to the center of at least one of four other first open windows obliquely adjacent to the one first open window. With the provision of the second open window, the channel width per unit area becomes wider than for a gate electrode having only the first open windows, resulting in a reduced on-resistance.

Abstract: A MOS type semiconductor device includes a thin-film semiconductor, a gate oxide film, and a gate. The thin-film semiconductor has a drain region, a source region, and a channel region arranged between these two regions. The gate oxide film is formed on the thin-film semiconductor. The gate is formed in correspondence with the channel region via the gate oxide film. The thin-film semiconductor is formed such that the film thickness of the drain region and the source region is made smaller than the film thickness of the channel region.

Abstract: Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

Abstract: A latch-up free insulated gate transistor includes an anode region electrically connected to an anode contact, a first base region on the anode region, a second base region on the first base region, connected to a cathode contact, an insulating region on the second base region and a field effect transistor on the insulating region, electrically connected between the cathode contact and the first base region. The field effect transistor provides an electrical connection between the first base region and the cathode contact in response to a turn-on bias signal. The insulating region prevents electrical conduction between the second base region and the field effect transistor and, in particular, suppresses minority carrier injection from the second base region to the source of the field effect transistor which is electrically connected to the cathode contact.

Abstract: The miniaturization of junction field effect transistors constituting memory cells and higher integration of a dynamic semiconductor memory device are attained. Word lines composed of a p-type impurity diffusion layer are formed on an n-type silicon substrate. An n-type impurity diffusion layer is formed within the p-type impurity diffusion layer. The n-type impurity diffusion layer constitutes two source-drain regions and a channel region, and the p-type impurity diffusion layer constitutes a gate region in each junction field effect transistor. The diffusion layer depth of the channel region is less than that of the source-drain regions. Bit lines are connected to one source-drain region, and storage nodes are connected to the other source-drain region. Each capacitor is made of a storage node, a dielectric film and a cell plate electrode.

Abstract: Field oxide films are formed on a semiconductor substrate of first conductivity type to be spaced from each other in the stripe shape. Gate insulating films are formed on the semiconductor substrate between the field oxide films. Word lines or control gate electrodes are formed on the field oxide films and the gate insulating films to be spaced from each other in the stripe shape along a direction perpendicular to the field oxide films. Grooves are formed in the gate insulating films and the field oxide films in regions sandwiched by the word lines. Source regions of second conductivity type are formed in the semiconductor substrate in the grooves formed in the gate insulating films. A common source wiring region of second conductivity type for electrically connecting the respective source regions is formed in the semiconductor substrate in the grooves formed in the field oxide films.

Abstract: A semiconductor body (1) has a first region (2) of one conductivity type adjacent one major surface (3). Second and third regions (5 and 6) of the opposite conductivity type are provided within the first region (2) adjacent the one major surface (3) and an insulated gate structure (80) overlies a conduction channel region (9) between the second and third regions (5 and 6) for providing a gateable connection along the length (L) of the conduction channel region (9) between the second and third regions (5 and 6). The insulated gate structure (80) has a gate insulating region (81) and a gate conductive region (82) extending on the gate insulating region (81) and up onto a relatively thick insulating region (4) adjoining the gate insulating region (81).

Abstract: A semiconductor delay circuit device comprises a pair of transistors of the same conduction type having source regions that are arranged adjacent to each other and facing each other, and a substrate contact diffusion region whose conduction type is opposite to that of the source regions. The substrate contact diffusion region extends between the source regions. Therefore, the source regions of the transistors do not influence each other.

Abstract: A silicon layer formed atop a sapphire substrate is selectively recrystallized such that the original degraded quality of the crystallinity of an N-well region where a P-channel device is to be formed is enhanced, so that leakage in the P-channel device is reduced, while the high ultraviolet reflectance number of a P-well region where an N-channel device resides remains unaffected. The process according to the present invention involves implanting silicon into only that portion of the silicon layer where an N-conductivity well region for a P-channel device is to be formed. An N-conductivity type impurity is introduced into the silicon-implanted portion of the silicon layer, to form the N-conductivity well region. The structure is then annealed at a relatively low temperature for several minutes, which is sufficient to activate the phosphorus and to cause local recrystallization of the N-well region of the silicon layer, without essentially causing a redistribution of the phosphorus.

Abstract: A Metal Insulator Semiconductor (MIS) heterojunction transistor. The MIS transistor is in a layered wafer having a n.sup.+ Si substrate, n Si collector layer, and a p Si/SiGe base. The base Si/SiGe interface may be vertical or horizontal. A thin oxide layer separates the base from the emitter, which is of a low work function metal such as Al, Mg, Mn, or Ti.

Abstract: In an n-channel heterojunction field effect transistor (HJFET) comprising a buffer region, a channel layer, and a carrier supplying layer which are deposited on a substrate in this order, the buffer region comprises a p-type GaAs layer, an undoped GaAs layer, and an n-type GaAs layer in this order. The p-type GaAs layer has substantially the same impurity concentration per unit area as the n-type GaAs layer. Holes are depleted in the whole of the buffer region at thermal equilibrium.