Abstract: A first power amplifier amplifies first transmission signals in a first frequency band and outputs the resultant signals. A first matching circuit includes a plurality of first inductor portions and is connected to an output pad electrode of the first power amplifier. A second power amplifier amplifies second transmission signals in a second frequency band higher than the first frequency band and outputs the resultant signals. A second matching circuit includes at least one second inductor portion and is connected to an output side of the second power amplifier. A multilayer substrate has a first main surface and a second main surface located opposite to each other and is provided with the first and second power amplifiers and the first and second matching circuits. The first inductor portion closer than the other first inductor portions to the output pad electrode includes an inner-layer inductor portion located in the multilayer substrate.

Abstract: A transimpedance amplifier circuit includes a single-input amplifier that converts a current signal into a voltage signal, a control current circuit that generates a control current based on the voltage signal and a reference voltage signal, and a bypass circuit. The bypass circuit includes a control circuit configured to receive the control current, a feedback current source configured to generate a direct current (DC) bypass current, and a variable resistance circuit configured to generate an alternating current (AC) bypass current. The control circuit includes a first current mirror circuit that varies the DC bypass current via the feedback current source in accordance with the control current, and a second current mirror circuit that varies the AC bypass current via the variable resistance circuit in accordance with the control current and an offset current.

Abstract: An envelope tracking integrated circuit having a tracker circuitry configured to generate a modulated supply voltage for a radio frequency power amplifier in response to an envelope of a radio frequency signal to be amplified by the radio frequency power amplifier is disclosed. Also included is a charge pump system configured to generate a tracker supply voltage for the tracker circuitry. Further included is an analog multiplexer configured to receive the tracker supply voltage and a battery source voltage and output a selected one of the tracker supply voltage and the battery source voltage in response to a voltage select signal. A digital processor further included in the envelope tracking integrated circuit is configured to control portions of the tracker circuitry and be powered by the selected one of the tracker supply voltage and the battery source voltage during transmission gaps when the radio frequency signal is not transmitted.

Abstract: A high frequency circuit includes a transmit terminal and a transmit and receive terminal, a power amplifier that amplifies a high frequency signal inputted from the transmit terminal and outputs the high frequency signal toward the transmit and receive terminal, and an output matching circuit that is positioned on a signal path connecting the power amplifier and the transmit and receive terminal and that optimizes the output load impedance of the power amplifier. The output matching circuit includes a matching circuit coupled to an output terminal of the power amplifier, another matching circuit, and a switch that changes a connection between the matching circuits. The power amplifier and the switch are formed at a single semiconductor IC. The matching circuits are formed outside the semiconductor IC.

Abstract: Device and method are disclosed for downlink gain compensation at a radio unit. According to an embodiment, the device comprises a pre-distortion circuit, a digital gain adjuster, a gain determiner and a first gain controller. The pre-distortion circuit is configured to generate and apply a pre-distortion to an input signal. The digital gain adjuster is configured to apply an adjustable gain to an output signal from the pre-distortion circuit. The gain determiner is configured to determine a gain difference between a target downlink gain and current downlink gain. The first gain controller is configured to control the digital gain adjuster based on the gain difference. A radio unit comprising the device is also disclosed.

Abstract: An apparatus includes an amplifier and a bias network. The amplifier generally has a predefined linear range. The bias network is generally connected to an input of the amplifier. The bias network generally comprises a linearizer configured to provide gain expansion and extend linearity of the amplifier beyond the predefined linear range.

Abstract: An amplifier circuit includes a first terminal and a second terminal, an amplifier disposed in a first path connecting the first terminal and the second terminal, a first switch circuit disposed in the first path between the amplifier and the second terminal, an attenuator disposed in the first path between the amplifier and the first switch circuit, and a second switch circuit disposed in a second path that is connected to the first terminal and the second terminal while bypassing the amplifier, the attenuator, and the first switch circuit.

Abstract: An amplifier circuit includes a first transistor including a signal input portion into which a signal is input from the outside, and a load inductor connected between the first transistor and a power supply line. In addition, the amplifier circuit includes a feedback circuit, which is connected between any position between the load inductor and the first transistor and the signal input portion of the first transistor. The gain and linearity are determined as appropriate in accordance with the amount of feedback from this feedback circuit.

Abstract: A radio frequency circuit has an amplifier that amplifies an input radio frequency signal, a power supply path that is disposed between an output node of the amplifier and a power supply node to which a DC bias voltage is supplied, and includes a first inductor and a second inductor connected in series, a first resonator that comprises a third inductor and a first capacitor connected in series to the third inductor, and resonates at a series resonance frequency, a second resonator that resonates at a series resonance frequency corresponding to an inductance of the first inductor, a capacitance of the second capacitor, and a resistance value of the first resistor, and a third resonator that comprises a third capacitor connected in parallel with the second inductor, and resonates at a parallel resonance frequency corresponding to a capacitance of the third capacitor and an inductance of the second inductor.

Abstract: A low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is configured to receive an input signal and to generate a bias signal. The first output stage circuit corresponding to a first wireless communication and is configured to be biased according to the bias signal and a first control signal, in order to generate a first output signal, in which the first control signal is for setting a first gain of the first output stage circuit. The second output stage circuit corresponding to a second wireless communication and is configured to be biased according to the bias signal and a second control signal, in order to generate a second output signal, in which the second control signal is for setting a second gain of the second output stage circuit.

Abstract: A power amplification system includes a Power Amplifier (PA) for amplifying an input RF signal. An adaptive bias circuit is configured to adaptively set a bias of the PA. The adaptive biasing circuit includes a gain expansion circuit, a gain compression circuit and a biasing circuit. The gain expansion circuit derives a gain-expansion control signal from the input RF signal. For a first sub-range of the input RF signal, the gain-expansion control signal has a larger dynamic range than the input RF signal. The gain compression circuit derives a gain-compression control signal from the input RF signal. For a second sub-range of the input RF signal having higher power levels than the first sub-range, the gain-compression control signal has a smaller dynamic range than the input RF signal. The biasing circuit sets the bias of the PA responsively to the gain-expansion control signal and the gain-compression control signal.

Abstract: Improved performance of analog computers is obtained by utilizing a deliberate reduction in gain of the gain elements present in the analog computer. While a prior output of the circuit (if any) is present, the gain of the gain elements is reduced to a level that is low enough that the input signal cannot propagate through the circuit. The input signal is then changed to a new value, or set of values, while the gain of the gain elements remains reduced. Finally, the gain of the gain elements is increased to a level that is high enough to allow the input signal to propagate through the circuit, resulting in an output that is a solution to the problem represented by the analog computer.

Abstract: A power amplifier module includes a power amplifier including an amplifying unit including an amplifying transistor configured to amplify an input signal and output an output signal, and a bias unit including a bias transistor configured to provide a bias current to the amplifying transistor, and a sub bias transistor configured to provide a sub bias current to the amplifying transistor; and a control unit configured to provide a control current to the bias transistor and the sub bias transistor. The control unit is further configured to vary the control current according to the sub bias current, and a level of the sub bias current is lower than a level of the bias current.

Abstract: An amplifier includes: a circuit pattern providing a plurality of signal paths having different lengths; a transistor chip; a plurality of pads of transistor cells, the pads being electrically connected to the circuit pattern and being arranged on the transistor chip; a plurality of the transistor cells; a plurality of transmission lines for connecting each of the plurality of pads and each of the plurality of transistor cells, the transmission lines being arranged on the transistor chip, and a plurality of harmonic processing circuits each connected to each of the plurality of transmission lines and arranged on the transistor chip. The plurality of harmonic processing circuits each has a capacitor and an inductor, and a product of the capacitance of the capacitor and the inductance of the inductor is made constant in each of the plurality of harmonic processing circuits.

Abstract: A semiconductor circuitry includes a first circuitry having a differential transistor pair and a pair of current sources connected in series to the differential transistor pair, a pair of transmission lines connected to the differential transistor pair at the opposite side to the current sources, and a second circuitry, connected to a node between the differential transistor pair and the current sources, and configured to test operations of at least the differential transistor pair and a latter-stage circuity connected to the transmission lines, in the state where the current outputs of the pair of current sources are stopped.

Abstract: An amplifier comprises a common emitter stage coupled to a first and a second input, a common base stage coupled to the common emitter stage and to a first and a second output, and a cancellation path coupled to the common emitter stage and the common base stage and to the first and second outputs. The cancellation path generates a first cancellation signal that is 180 degrees out of phase with a first leakage signal at the first output and a second cancellation signal that is 180 degrees out of phase with a second leakage signal at the second output. The cancellation path comprises a first cancellation transistor coupled to the common emitter stage and the common base stage and to the first output and a second cancellation transistor coupled to the common emitter stage and the common base stage and to the second output.

Abstract: An electronic device including an amplifier which includes a first transistor configured to receive an input signal through a gate terminal thereof and having a source terminal electrically connected to ground, a second transistor configured to transmit an output signal through a drain terminal thereof and having a gate terminal electrically connected to the ground, and a switch electrically connected to the gate terminal of the second transistor and configured to switch a voltage being supplied to the gate terminal of the second transistor in accordance with turn-on or turn-off of the amplifier.

Abstract: Distributed amplifiers with controllable linearization are provided herein. In certain embodiments, a distributed amplifier includes a differential input transmission line, a differential output transmission line, and a plurality of differential distributed amplifier stages connected between the differential input transmission line and the differential output transmission line at different points or nodes. The distributed amplifier further includes a differential non-linearity cancellation stage connected between the differential input transmission line and the differential output transmission line and providing signal inversion relative to the differential distributed amplifier stages. The differential non-linearity cancellation stage operates with a separately controllable bias from the differential distributed amplifier stages, thereby providing a mechanism to control the linearity of the distributed amplifier.

Abstract: A receiver front-end includes a first peaking gain stage configured to amplify a received differential pair of signals received on an input differential pair of nodes. The first peaking gain stage has a first frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency. A second peaking gain stage is configured to amplify a differential pair of signals generated by the first peaking gain stage. The second peaking gain stage has a high input impedance and a second frequency response including a second peak gain at or near the carrier frequency in a second pass band. The second peak gain occurs just prior to a second cutoff frequency. The first peaking gain stage and the second peaking gain stage have a cascaded peak gain at or near the carrier frequency.

Abstract: An apparatus that includes a tracking amplifier having an amplifier output terminal coupled to an output voltage node and an envelope input terminal configured to receive an envelope signal of a radio frequency signal is disclosed. A multi-level voltage converter has a switched voltage terminal coupled to the output voltage node and a converter control input terminal configured to receive a converter control signal. A control signal multiplexer has a converter control output terminal coupled to the converter control input terminal, a first converter signal input terminal configured to receive a first converter control signal corresponding to a lower envelope modulation bandwidth, a second converter signal input terminal configured to receive a second converter control signal corresponding to a higher envelope modulation bandwidth, and a converter control signal selector terminal configured to receive a control selector signal for selecting between the first and second converter control signals.