Patents Examined by Suian Tang
  • Patent number: 8878167
    Abstract: An organic light emitting diode lighting equipment includes a transparent substrate main body, a first electrode formed on the substrate main body, a subsidiary electrode formed on the first electrode to partition the first electrode at a predetermined distance, an organic emissive layer formed on the first electrode, and a second electrode formed on the organic emissive layer. The subsidiary electrode has an inclined lateral side facing toward the organic emissive layer.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyuk-Sang Jun, Ok-Keun Song, Young-Mo Koo, Jung-Ha Lee, Il-Hwa Hong
  • Patent number: 8853785
    Abstract: An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; a portion of at least one electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged at least between the portion of the electrically conductive material and the channel region of the second transistor; and a section of the channel region of the second transistor in a plane parallel to the two primary faces of the semiconductor layer is included in a section of the portion of the electrically conductive material projected in said plane.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: October 7, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Emmanuel Augendre, Maud Vinet, Laurent Clavelier, Perrine Batude
  • Patent number: 8575726
    Abstract: A semiconductor device includes: a semiconductor chip including: a first main face having an edge portion, a second main face locating the opposite side to the first main face, a crystalline defect region present within a region including at least the edge portion being adjacent to the first main face, the crystalline defect region being configured to have lower stress than the stress in the other semiconductor region for the same strain; and a metallic substrate to be bonded via a bonding member to the first main face of the semiconductor chip.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: November 5, 2013
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Yoshinori Murakami
  • Patent number: 8508025
    Abstract: A multiple die package includes a folded leadframe for interconnecting at least two die attached to another leadframe. In a synchronous voltage regulator the folded leadframe, which is formed from a single piece of material, connects the high side switching device with the low side switching device to provide a low resistance, low inductance connection between the two devices.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: August 13, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Tiburcio A. Maldo, Hua Yang
  • Patent number: 8507299
    Abstract: The present invention relates to a light emitting diode package and a manufacturing method thereof. The light emitting diode package includes a substrate, an LED chip mounted on an upper part of a substrate, a molding material coated at the upper part of the substrate including an external surface of the LED chip, and an encapsulant coated at a lower part of the substrate and can improve luminous efficiency, minimize a package failure, and reduce a manufacture cost by facilitating the manufacturing process.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong Ah Joo, Chang Hoon Kwak, Na Na Park, Il Woo Park
  • Patent number: 8471283
    Abstract: A white LED lamp including: a conductive portion; a light emitting diode chip mounted on the conductive portion, for emitting a primary light having a peak wavelength of 360 nm to 420 nm; a transparent resin layer including a first hardened transparent resin, for sealing the light emitting diode chip; and a phosphor layer covering the transparent resin layer, the phosphor layer being formed by dispersing a phosphor powder into a second hardened transparent resin, and the phosphor powder receiving the primary light and radiating a secondary light having a wavelength longer than that of the primary light. An energy of the primary light contained in the radiated secondary light is 0.4 mW/lm or less. In the white LED lamp, a backlight, and an illumination device using the white LED lamp an amount of UV light to be contained in the released light and an amount of heat to be generated from the lamp are decreased to be small.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: June 25, 2013
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Materials Co., Ltd.
    Inventors: Tsutomu Ishii, Hajime Takeuchi, Yasumasa Ooya, Katsutoshi Nakagawa, Yumi Ito, Masaki Toyoshima, Yasuhiro Shirakawa, Ryo Sakai
  • Patent number: 8461623
    Abstract: A power semiconductor module (1) includes a first MOS transistor (16) connected to a positive side power supply terminal via a first conductor pattern (11), a first free wheeling diode (17) connected to the positive side power supply terminal via a second conductor pattern (12), a second MOS transistor (18) connected to a negative side power supply terminal via a third conductor pattern (13), and a second free wheeling diode (19) connected to the negative side power supply terminal via a fourth conductor pattern (14). These semiconductor elements (16-19) are connected to a load side output terminal via a common fifth conductor pattern (15). The semiconductor element (16, 17) connected to the positive side power supply terminal and the semiconductor element (18, 19) connected to the negative side power supply terminal are arranged alternately, substantially linearly.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: June 11, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shuhei Nakata
  • Patent number: 8324709
    Abstract: A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Atsuki Ono
  • Patent number: 8326008
    Abstract: A method for determining the area of an analysis chamber covered by a biologic fluid sample quiescently residing within the chamber is provided. The chamber has a first panel with an interior surface, and a second panel with an interior surface, both of which panels are transparent.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: December 4, 2012
    Assignee: Abbott Point of Care, Inc.
    Inventors: Niten V. Lalpuria, Stephen C. Wardlaw
  • Patent number: 8309889
    Abstract: An indicating lamp is provided on the exterior of a vent port to indicate failure of a heater within the vent port. An electrical circuit is provided to energize the indicating lamp in response to failure of one or the other of a pair of heaters within the vent port.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: November 13, 2012
    Assignee: Component Hardware Group, Inc.
    Inventor: Thomas Graham
  • Patent number: 8304832
    Abstract: A semiconductor device with increased freedom of wirings and a manufacturing method thereof are provided by enabling favorable connection between an upper wiring layer and a lower wiring layer through a semiconductor element. The semiconductor device includes: a first insulating layer over an insulating substrate; a first wiring layer and a second insulating layer on the first insulating layer; a single crystal semiconductor layer including a channel region and an impurity region, on the first wiring layer and the second insulating layer; a gate electrode over the channel region with a gate insulating layer interposed therebetween; a third insulating layer covering the first wiring layer, the single crystal semiconductor layer, and the gate electrode; and a second wiring layer over the third insulating layer. The first wiring layer is in contact with the impurity region, and the first and wiring layers are electrically connected to each other.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8295568
    Abstract: An medical image display processing apparatus capable of easily displaying an axial image of a body part desired by a user from among one series of axial images acquired by imaging an object to be inspected with a modality. The medical image display processing apparatus includes a part recognition unit for recognizing a body part shown in each of one series of axial images; and a display processing unit for causing the display unit to display an axial image included in the one series of axial images, and causing, when receiving a body part change instruction, the display unit to display an axial image showing a different part from the part of the axial image being displayed on the display unit based on a recognition result of the part recognition unit.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: October 23, 2012
    Assignee: FUJIFILM Corporation
    Inventor: Hideyuki Sakaida
  • Patent number: 8295506
    Abstract: Systems and methods are disclosed for capturing sound for communication by mounting one or more intra-oral microphones to capture sound; and mounting a mouth wearable communicator in the oral cavity to communicate sound with a remote unit.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 23, 2012
    Assignee: Sonitus Medical, Inc.
    Inventors: Reza Kassayan, John Spiridigliozzi
  • Patent number: 8283657
    Abstract: A sensor and/or actuator system in which functional circuitry is embedded in an all organic electromechanical transducer device is disclosed. The electromechanical transducer device exploits the behavior of a flexible sensible ionomeric material sheet as effective sensing or actuating member sandwiched between flexible organic electrodes when undergoing a deformation or being polarized at a certain drive voltage applied to the, electrodes, respectively. The completely embedded all organic system is realized with a process exploiting relatively low cost deposition and patterning techniques. The enhanced flexibility makes the all organic device suitable for new applications in fields ranging from biomedical to aerospace industry.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: October 9, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Manuela La Rosa, Luigi Fortuna, Salvatore Graziani, Donata Rosaria Maria Nicolosi, Giovanni Sicurella
  • Patent number: 8280074
    Abstract: An audio signal processing apparatus for outputting an input digital audio signal as a positive phase PWM signal and a negative phase PWM signal. The resolution of the input digital audio signal is converted to a low resolution and noise shaping is performed to generate a positive phase digital signal (REF_P) and a negative phase digital signal (REF_N). Both signal patterns are compared at a buffer and pattern comparator section when muting. If the signal patterns match, a selector outputs a set value having 50% duty instead of the digital signals to optimize timing for switching to 50% duty when muting.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Yasunori Yamamoto
  • Patent number: 8253237
    Abstract: A power semiconductor arrangement and method is disclosed. One embodiment provides a power semiconductor module. An insulator is arranged between the module and a cooling element, increasing clearances between the power semiconductor module and the cooling element.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: August 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Peter Kanschat, Thilo Stolze
  • Patent number: 8237491
    Abstract: A semiconductor device includes a first conductive type first transistor, a first conductive type second transistor, a first power supply pad arranged between the first transistor and the second transistor and supplying a first potential, a second conductive type third transistor, a second conductive type fourth transistor, a second power supply pad arranged between the third transistor and the fourth transistor and supplying a second potential, a first output pad arranged between the first transistor and the third transistor, and a second output pad arranged between the second transistor and the fourth transistor, in which a direction in which a line connecting the first power supply pad with the second power supply pad extends is perpendicular to a direction in which a line connecting the first output pad with the second output pad extends.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Norihiko Araki
  • Patent number: 8237215
    Abstract: An SOI device includes an SOI substrate having a structure in which a first buried oxide layer and a silicon layer are stacked in turn over a semiconductor substrate. A gate is formed over the silicon layer of the SOI substrate. A second buried oxide layer is formed at both sides of the gate in a lower portion of the silicon layer so that a lower end portion of the second buried oxide layer is in contact with the first buried oxide layer. A junction region is then formed in the portion of the silicon layer above the second buried oxide layer so that the lower end portion of the junction region is in contact with the second buried oxide layer.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong Taik Kim, Tae Su Jang
  • Patent number: 8222671
    Abstract: This invention generally relates to power semiconductor devices, and in particular to improved thyristor devices and circuits. The techniques we describe are particularly useful for so-called MOS-gated thyristors. We describe a thyristor comprising a plurality of power thyristor devices connected in parallel, each said thyristor device being operable at a device current which the device has an on-resistance with a positive temperature coefficient.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: July 17, 2012
    Assignee: Cambridge Enterprises Limited
    Inventors: Patrick Reginald Palmer, Zhihan Wang
  • Patent number: 8188585
    Abstract: An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: May 29, 2012
    Assignee: Infineon Technologies AG
    Inventors: Markus Brunnbauer, Harry Hedler, Thorsten Meyer