Abstract: A wafer-scale assembly apparatus for integrated circuits and a method for forming the wafer-scale assembly are disclosed. A semiconductor wafer including a plurality of circuits is provided with a plurality of metal contact pads as electrical entry and exit ports. A first wafer-scale patterned polymer film carrying solder balls for each of the contact pads on the wafer is positioned opposite the wafer, and the wafer and the film are aligned. The film is brought into contact with the wafer. Radiant energy in the near infrared spectrum is applied to the backside of the wafer, heating the wafer uniformly and rapidly without moving the semiconductor wafer. Thermal energy is transferred through the wafer to the surface of the wafer and into the solder balls, which reflow onto the contact pads, while the thermal stretching of the polymer film is mechanically compensated. The uniformity of the height of the liquid solder balls is controlled either by mechanical stoppers or by the precision linear motion of motors.

Abstract: A semiconductor device is disclosed, which can extend an effective channel length without changing layout. The semiconductor device includes a device barrier film formed in a semiconductor substrate, for defining an active region, a channel region formed in the semiconductor substrate at a variable depth and defined by removing some of the semiconductor substrate corresponding to the active region in a groove form, and a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween, a material of the gate electrode being covered with the gate insulating film.

Abstract: A semiconductor device having a dielectric layer formed between a first and a second conductive layer. The dielectric layer comprising a layer of silicon oxide, SiOX≦2, having a dielectric constant greater than about 3.9 and less than or equal to about 12.

Abstract: Embodiments provide a method, article of manufacture, and apparatus for providing a component package for components such as integrated circuits. In one embodiment, a carrier includes a plurality of sidewalls formed thereon to form a component package assembly. In one aspect, a cover is bonded to the component package assembly to form a plurality of separable individual component packages having a cavity therein, where each individual component package encapsulates at least one component disposed on the carrier. The component package assembly is then separated into individually packaged devices.

Abstract: According to one embodiment of the present invention, a method for determining the location of contaminants on a semiconductor wafer comprises obtaining a first particle count of the wafer, scrubbing the wafer, obtaining a second particle count of the wafer after scrubbing the wafer, and determining the location of the particles based on the first and second particle counts. According to another embodiment of the present invention, a method for determining the source of particle contaminants in a semiconductor processing tool comprises the steps of obtaining a first particle count of a wafer with at least one film deposited thereon, scrubbing the wafer, obtaining a second particle count of the wafer after scrubbing the wafer, and localizing areas of the processing tool where the particle contamination originates from.

Abstract: A method for manufacturing a high dielectric constant insulating film made of a metal oxide on a silicon substrate is provided using a material gas mixture containing an oxidizing agent without forming silicon oxide layer on a silicon substrate. The manufacturing method includes the steps of placing the semiconductor substrate into a reaction chamber; introducing an organic metal material, oxidizing agent, and a material having a reducing action; and forming a high dielectric constant gate insulating film on the semiconductor substrate by a chemical reaction in the reaction chamber.

Abstract: Disclosed are methods and systems for forming salicide, in which a semiconductor substrate is provided with at least one exposed silicon surface. The semiconductor substrate is placed into a sputtering chamber. A silicide-forming metal layer, formed of a metal such as Co, Ni, is sputter-deposited over the exposed silicon surface. A process temperature is controlled below room temperature during the sputter deposition and preferably between approximately 0° C. to 10° C. The silicide-forming metal layer formed on the exposed silicon surface is first annealed to convert the silicide-forming metal layer into a salicide layer. Also, the system of the present invention is comprised of a sputter chamber including a mount for mounting a semiconductor substrate and a cooling mechanism coupled with the mount for cooling the semiconductor substrate. The cooling mechanism includes a controller to maintain a process temperature below room temperature.

Abstract: Alternative methods for making memory cards for computers and such eliminate a need for a separate external housing and a separate chip encapsulation step and enable more memory to be packaged in a same-sized card. One of said methods includes providing a substrate having opposite first and second surfaces with a memory chip mounted on and in electrical connection with a first surface of said substrate. Said second surface of said substrate is temporarily attached to a first surface of a flat carrier sheet, e.g., an adhesive tape. In one embodiment, a mold having a cavity therein is placed on said first surface of said carrier sheet such that said chip and said first surface of said substrate are enclosed in said cavity between said mold and said carrier sheet. A fluid plastic is introduced into said cavity and cured to encapsulate said chip and at least said first surface of said substrate in a protective, monolithic body of hardened plastic. A completed card is then detached from said carrier sheet.

Abstract: A method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding like an overhang, wherein every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern.

Abstract: A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

Abstract: A solid-state pickup element achieves both improvement in sensitivity and reduction of pixel size and a method thereof, includes a first conductive type semiconductor area, which is formed at least so as to include the inside of the semiconductor substrate upward of the overflow barrier area inside the semiconductor substrate, and a charge accumulating area at the position corresponding to the first conductive type semiconductor area of the light receptive sensor part in the epitaxial layer on the semiconductor substrate. An overflow barrier area is formed in the semiconductor substrate, and the first conductive type semiconductor area is formed on the surface, respectively, wherein an epitaxial layer is formed on the semiconductor substrate, and a charge accumulating area is formed at the position corresponding to the first conductive type semiconductor area on the surface side of the epitaxial layer, thereby producing a solid-state pickup element.

Abstract: A method for manufacturing a thick oxide layer on a semiconductive substrate is presented. The method comprises the formation of at least one layer of dielectric material on said substrate, followed by formation of a plurality of trench regions of a predetermined width in the substrate. A plurality of corresponding walls of semiconductive material of a second predetermined width are delimited. Finally, the semiconductor is submitted to a thermal treatment to oxidize said walls.

Abstract: A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.

Abstract: Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed an etch stop layer interposed between a first dielectric layer and second dielectric layer within a non active product region of a substrate, but not within an active product region of the substrate. Within the dual damascene method, an endpoint for forming a trench within a dual damascene aperture within the active product region is sensed by reaching the etch stop layer when forming a dummy trench within the non active product region.

Abstract: The present invention is disclosed a microchannel array structure embedded in a silicon substrate and a fabrication method thereof. The microchannel array structure of the present invention is formed deep inside the substrate and has high-density microscopic micro-channels. Besides, going through surface micromachining, physical and chemical properties of the silicon substrate are hardly influenced by the fabrication procedures. With microchannels buried in the substrate, the top of a microchannel array structure becomes flat, minimizing the effect of step height. That way, additional devices such as passive components, micro sensors, micro actuators and electronic devices can be easily integrated onto the microchannel array structure.

Abstract: The tradeoff between breakdown voltage and on-resistance for LDMOS devices has been improved by having two epitaxial N−regions instead of the single epitaxial N−region that is used by devices of the prior art. The resistivities and thicknesses of these two N−regions are chosen so that their mean resistivity is similar to that of the aforementioned single N−layer. A key feature is that the lower N−layer (i.e. the one closest to the P−substrate) has a resistivity that is greater than that of the upper N−layer. If these constraints are met, as described in greater detail in the specification, improvements in breakdown voltage of up to 60% can be achieved without having to increase the on-resistance. A process for manufacturing the device is also described.

Abstract: A semiconductor inductor and a method for making a semiconductor inductor are provided. An oxide layer disposed over a substrate is etched to form an interconnect metallization trench within the oxide layer. The oxide layer is also etched to form a first inductor trench within the oxide layer such that the first inductor trench is defined in an inductor geometry. The oxide layer is then etched to form at least one via in the interconnect metallization trench and a second inductor trench over the first inductor trench in the oxide layer. The second inductor trench also has the inductor geometry. After the oxide layer is etched, the at least one via, the second inductor trench, the interconnect metallization trench and the first inductor trench are filled with copper. The semiconductor inductor is configured to have a low resistance and a high quality factor.

Abstract: A semiconductor device (10) having a stacked-gate buffer (30) wherein the stacked-gate buffer (30) has a substrate (65) and a top substrate region (70) both with the same first conductivity type. The buffer (30) also has two transistors (95.105), each with a current carrying electrode and a control electrode (90, 100). A deep doped region (120) lies between the first (90) and second (100) control electrodes where the deep doped region (120) is another current carrying electrode for the first transistor (95) and another current carrying electrode for the second transistor (105) and the deep doped region (120) has a second conductivity that is opposite the first conductivity type. A deeper doped region (80) is also part of the stacked-gate buffer which has a second conductivity type and lies between the first (90) and second (100) control electrodes and is deeper than the deep doped region (120). A method of forming the device is also provided herein.

Abstract: DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a planar construction and can be produced together with gate electrodes of transistors of a periphery of the cell arrangement. A depression of the substrate is provided per memory cell, a storage node of a storage capacitor being arranged in the lower region of said depression and a gate electrode of a vertical transistor being arranged in the upper region of said depression. The depressions of the memory cells are arranged between trenches filled with isolating structures. Upper source/drain regions of the transistors are arranged between two mutually adjacent isolating structures and between two mutually adjacent depressions. Lower source/drain regions are arranged in the substrate and adjoin the storage nodes. For process steps, alignment tolerances are so large that the space requirement for the memory cell can amount to 4F2.

Abstract: Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.